130 Register-Based Programming Appendix B

Interrupt Source

Register
Eight events can be enabled to interrupt the digitizer. These events are listed
in the above Interrupt Control Register definition for bits 8 through 15. The
Interrupt Source Register contains the latched version (bits 8-15) and the
unlatched version (bits 0-7) of these sources. The value of a source is
latched high when the source has a low-to-high transition.
The latched bits are cleared if they are masked as an interrupt source or by
reading the register and writing back the contents. Writing a “1” to the bit
clears the latch. The non-latched state of the interrupts is available all the
time. The bit ordering of the latched bits and the unlatched bits is the same
as the mask.

CVTable Channel 1

Register
This register holds the last value of the 2’s complement data stored in FIFO
for channel 1. Data is 14 bits with the LSB at bit 2.

CVTable Channel 2

Register
This register holds the last value of the 2’s complement data stored in FIFO
for channel 2. Data is 14 bits with the LSB at bit 2.
base + 0E16 15 14 13 12 11 10 9876543210
Read TRIG DONE PRE OVER CH4 CH3 CH2 CH1 TRIG DONE PRE OVER CH4 CH3 CH2 CH1
READ BITS (Interrupt Source Register)
bit 15, 7 TRIG A trigger has been received after pre-trigger acquisition is complete and
measurement count is not complete.
bit 14, 6 DONE Memory is full or post-trigger acquisition is complete.
bit 13, 5 PRE Pre-trigger data has been acquired and waiting for trigger.
bit 12, 4 OVER A dangerous OVERvoltage caused the channel input relay to open.
bit 11, 3 CH4 Channel 4 exceeded the set limit during the last sample taken.
bit 10, 2 CH3 Channel 3 exceeded the set limit during the last sample taken.
bit 9, 1 CH2 Channel 2 exceeded the set limit during the last sample taken.
bit 8, 0 CH1 Channel 1 exceeded the set limit during the last sample taken.
base + 1016 15 14 13 12 11 10 9876543210
Read MSB LSB 0 0
base + 1216 15 14 13 12 11 10 9876543210
Read MSB LSB 0 0