Interrupt Source Register

Eight events can be enabled to interrupt the digitizer. These events are listed in the above Interrupt Control Register definition for bits 8 through 15. The Interrupt Source Register contains the latched version (bits 8-15) and the unlatched version (bits 0-7) of these sources. The value of a source is latched high when the source has a low-to-high transition.

The latched bits are cleared if they are masked as an interrupt source or by reading the register and writing back the contents. Writing a “1” to the bit clears the latch. The non-latched state of the interrupts is available all the time. The bit ordering of the latched bits and the unlatched bits is the same as the mask.

base + 0E16

15

14

13

12

 

11

10

9

8

7

6

 

5

4

3

2

1

0

Read

 

TRIG

DONE

PRE

OVER

CH4

CH3

CH2

CH1

TRIG

DONE

 

PRE

OVER

CH4

CH3

CH2

CH1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ BITS (Interrupt Source Register)

 

 

 

 

 

 

 

 

 

 

 

 

bit 15, 7

 

TRIG

A trigger has been received after pre-trigger acquisition is complete and

 

 

 

 

 

 

measurement count is not complete.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 14, 6

 

DONE

Memory is full or post-trigger acquisition is complete.

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 13, 5

 

PRE

Pre-trigger data has been acquired and waiting for trigger.

 

 

 

 

 

 

 

 

 

 

bit 12, 4

 

OVER

A dangerous OVERvoltage caused the channel input relay to open.

 

 

 

 

 

 

 

 

 

bit 11, 3

 

CH4

Channel 4 exceeded the set limit during the last sample taken.

 

 

 

 

 

 

 

 

 

 

bit 10, 2

 

CH3

Channel 3 exceeded the set limit during the last sample taken.

 

 

 

 

 

 

 

 

 

 

bit 9, 1

 

CH2

Channel 2 exceeded the set limit during the last sample taken.

 

 

 

 

 

 

 

 

 

 

bit 8, 0

 

CH1

Channel 1 exceeded the set limit during the last sample taken.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CVTable Channel 1 Register

This register holds the last value of the 2’s complement data stored in FIFO for channel 1. Data is 14 bits with the LSB at bit 2.

base + 1016

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Read

MSB

 

 

 

 

 

 

 

 

 

 

 

 

LSB

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CVTable Channel 2 Register

This register holds the last value of the 2’s complement data stored in FIFO for channel 2. Data is 14 bits with the LSB at bit 2.

base + 1216

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Read

MSB

 

 

 

 

 

 

 

 

 

 

 

 

LSB

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

130 Register-Based Programming

Appendix B

Page 130
Image 130
Agilent Technologies E1564A, E1563A Interrupt Source Register, CVTable Channel 1 Register, CVTable Channel 2 Register

E1563A, E1564A specifications

Agilent Technologies, a prominent player in the field of electronic measurement, offers a range of products designed for various testing applications. Among their notable offerings are the E1564A and E1563A modules. Both models are designed for high-performance testing and measurement, catering particularly to the needs of engineers and technicians in the telecommunications and wireless industries.

The Agilent E1564A is a high-speed data and synchronization generation module, specifically tailored for advanced signal analysis. One of its primary features is its ability to provide a wide range of modulation types, including QPSK and 16QAM, which are essential for testing modern communication systems. The module also boasts a flexible output that supports multiple channels, making it efficient for testing complex systems where multiple data streams are present. Its exceptional performance in generating accurate waveforms enables engineers to perform thorough tests and validations on their devices.

On the other hand, the E1563A module is predominantly focused on protocol analysis and provides engineers with insights into the behavior of their communication systems. This module features comprehensive support for various communication protocols, making it invaluable when debugging and validating designs. Engineers can utilize the extensive measurement capabilities of the E1563A to analyze data integrity and system performance, ensuring that their products meet required specifications.

Both modules leverage advanced technologies from Agilent, ensuring high accuracy and reliability in measurements. They are equipped with powerful processing capabilities that allow for real-time data analysis, a critical aspect when working with high-frequency signals. Furthermore, these modules are designed for seamless integration into Agilent’s test and measurement platforms, enhancing usability and facilitating complex testing scenarios.

In summary, the Agilent E1564A and E1563A modules represent cutting-edge solutions for engineers involved in testing and validating communication systems. With their robust features, including support for various modulation schemes and protocol analysis, these modules enable efficient and accurate measurements. The commitment to quality and precision from Agilent Technologies continues to make these devices essential tools in the industry, helping engineers push the boundaries of innovation in telecommunications.