![](/images/new-backgrounds/1022145/22145271x1.webp)
Trigger/Interrupt
Level Channel 4
Register
This register provides
| base + 2E16 | 15 | 14 | 13 |
| 12 | 11 | 10 | 9 | 8 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| Write* |
| D6 | D5 |
| D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | GL |
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| Read** |
| D6 | D5 |
| D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | GL |
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| *WRITE/**READ BITS (Trigger/Interrupt Level Channel 4 Register) |
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| bit 0 |
| GL |
| Greater than or Less than; “0” = >, “1” = <. |
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| bits |
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| data bits. |
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Sample Period High This register provides the high byte of the sample period.
Byte Register
base + 3016 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Write* |
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| x | x | x | x | x | x | x | x |
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Read** | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | x | x | x | x | x | x | x | x |
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Sample Period Low This register provides the low word (2 bytes) of the sample period.
Word Register
base + 3216 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Write* | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | LSB |
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Read** | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | LSB |
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Pre-Trigger Count High Byte Register
base + 3416 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Write |
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| undefined |
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| C5 | C4 | C3 | C2 | C1 | C0 | |
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Read | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | C5 | C4 | C3 | C2 | C1 | C0 |
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136 | Appendix B |