DCC Interface Transmit Timing | Agilent Technologies HDMP-3001

8.6 TOH Interface E1/E2/F1 Receive Timing

RX_E1E2F1_CLK

tVE1FC

tHE2FC

tHF1FC

RX_E1_DATA

RX_E2_DATA

RX_F1_DATA

Figure 34. TOH Interface E1/E2/F1 Receive Timing

Label	Parameter	Min	Typ.	Max	Units
RX_E1E2F1_CLK	TX_E1E2F1_CLK frequency		64		kHz

tVE1FC	Transition RX_E1_DATA from RX_E1E2F1_CLK low	30		70	ns
tHE2FC	Transition RX_E2_DATA from RX_E1E2F1_CLK low	30		70	ns
tHF1FC	Transition RX_F1_DATA from RX_E1E2F1_CLK low	30		70	ns

8.7 DCC Interface Transmit Timing

TX_SDCC_CLK

TX_LDCC_CLK

tSSDCTC tHSDFC

tSLDCTC tHLDFC

TX_SDCC_DATA

TX_LDCC_DATA

Figure 35. DCC Interface Transmit Timing

Label	Parameter	Min	Typ.	Max	Units
TX_SDCC_CLK	TX_SDCC_CLK frequency		192		kHz

tSSDCTC	Setup TX_SDCC_DATA to TX_SDCC_CLK high	100			ns
tHSDFC	Hold TX_SDCC_DATA from TX_SDCC_CLK high	100			ns
TX_LDCC_CLK	TX_LDCC_CLK frequency		576		kHz

tSLDCTC	Setup TX_LDCC_DATA to TX_LDCC_CLK high	100			ns
tHLDFC	Hold TX_LDCC_DATA from TX_LDCC_CLK high	100			ns

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Agilent Technologies HDMP-3001 manual TOH Interface E1/E2/F1 Receive Timing, DCC Interface Transmit Timing

HDMP-3001 specifications

Agilent Technologies, a prominent name in electronics and measurement technology, offers a wide range of products that cater to various industries. Among its notable offerings is the HDMP-3001, a high-speed, serial data transceiver designed to facilitate robust communications in electronic systems. The HDMP-3001 stands out with its ability to handle high bandwidths, making it particularly suited for applications requiring rapid data transfer, such as telecommunications, computer networking, and high-performance computing.

One of the main features of the HDMP-3001 is its advanced signaling technology. By employing differential signaling, the transceiver minimizes electromagnetic interference and enhances signal integrity. This is crucial in environments with multiple electronic devices operating simultaneously, as it ensures data is transmitted clearly and without degradation.

The HDMP-3001 operates at a maximum data rate of 1 Gbps, allowing for efficient data transfer over short distances. This capability is coupled with a flexible architecture that enables users to configure the transceiver for various applications. The device supports both point-to-point and point-to-multipoint configurations, giving engineers the versatility they need in designing communication links.

Moreover, the HDMP-3001 features on-chip clock recovery functionality, which simplifies system design by reducing the number of external components needed. This built-in feature allows the transceiver to maintain synchronization even as data rates increase, further enhancing performance.

The low power consumption characteristic of the HDMP-3001 is another notable advantage. This makes it an attractive choice for battery-operated devices and systems where power efficiency is critical. The transceiver’s design ensures optimal performance while minimizing heat generation and power draw, enabling longer operational lifetimes.

In terms of physical characteristics, the HDMP-3001 comes in a compact, surface-mount package, allowing for easier integration into various circuit board designs. The small form factor, combined with its innovative technology, makes it a popular choice among engineers seeking to improve data transmission reliability without compromising on space or power constraints.

Overall, Agilent Technologies' HDMP-3001 is a formidable solution for high-speed serial data transmission, characterized by its robust performance, low power consumption, and versatile configuration options. With these features, it continues to be an essential component in the evolving landscape of electronic communications.

Contents

Agilent HDMP-3001 117 110116 118 112 104105 113 STS-3c/STM-1 Configuration for List of Tables Internal Functional Blocks See the block diagramHDMP-3001 Features List Full Duplex Fast Ethernet Interfaces ApplicationsBenefits Data Processing Pinout Pin Assignments Receive Line Alarm Indication Signal Output Receive Loss of Frame OutputContinues Signal name Pin # TypeI/O Signal description Loss of Sonettx clockLoss of Sonetrx clock Received E1/E2/F1 Data Reference Clock a Received Line DCC Data Drop output for received Transmit Line DCC Data Input for the Line Data Transmit Section DCC Data Input for the SectionTransmit Section DCC Reference Clock BUS Interface Mode Read Enable Active low Write Enable Active low GPIO0 SCLSDA GPIO1 Dgnd VDDDvdd PRXDMTXD1 PRXDMTXD2 PRXDMTXD3 Prxdvmtxen Prxermtxer INT I/O Buffer TypesBuffer types Buffer Type Name Comment TMS, TRSTB, TDI MII Management Interface IntroductionInterface Descriptions Microprocessor Interface Eeprom Interface Software State Machine Reset Initialization Hardware resetSoftware Reset Bit Order GFP Mode Laps Mode Performance Monitoring Test Loopbacks Loopbacks Polled Mode Jtag pins Signal Name DescriptionInterrupt Driven Mode Jtag Apsintb Laps Processing GFP Processing FCS Polynomial for Laps ProcessingLaps Scrambling FCS Polynomial for GFP Processing GFP Scrambling SONET/SDH Processing Ing Overview 3.1 SPE/VC Structure Path Trace J1 Signal Label C23.2 POH Path BIP-8 B3 Prdiauto Prdienh Rxpais Rxuneq Rxplm Rxlop Section Growth/Spare ZO Section Trace STS-3c/STM-1 TOH/SOH Row ColumnPointer Action Byte H3 Section BIP-8 B1 Synchronization Status S1 Line/MS BIP-24 B2APS Channel and Line/MS AIS/RDI K1 and K2 Line/MS REI M1 Transport Overhead Monitoring 4.2.5 B2 Error Counting4.1 LOC 4.2.1 J0 Monitoring 4.2.11 M1 Monitoring APS Monitoring4.2.10 S1 Monitoring Transport Overhead Drop Pointer Interpretation Current accepted pointer value is incremented by 1 modPointer Processing Path Overhead Monitoring MonitorSupports two methods Pattern Acceptance and Com Path REI Monitoring Path RDI MonitoringSTS-3C/STM-1 Framer If the framer is bypassed Framer Enabled DetailsFramer Bypass Details Descrambling 4.14 B1 Monitor SDH and Sonet mode Chip setup and configuration Eeprom DetectionConfigurations PHY and MAC mode Laps and GFP mode Active value of 0. Refer to Figure WRB WE0 RDB Rdyb Intb HDMP-3001 Pin Name Microprocessor Pin NameBusmode Cpuclk Clkout Eeprom Interface Configuration COL VSS Register Definitions MII Management Register Map Bit Type Bit Name Default value Description Chip Register Map SONET/SDH Transmit Registers Address Register Name SONET/SDH Transmit Registers SONET/SDH Receive Registers Address Register Name Ethernet Transmit Registers Txsapimsb Ethernet Receive Registers Address Register Name Latch State Global CNT ResetValue After Reset ADDR=0x001 Test Modes Bit Sdapu DISCHIPREV30 PHYADDR40 Rxaps Sumint INT ADDR=0x008 Summary Interrupt Mask Bit ADDR=0x007 Event Summary BitTohdsum Apsintb Mask ADDR=0x00A Rx Event Summary Mask Bit ADDR=0x009 Mode of Operation BitIsolate SONET/SDH PHY/MAC GFP/LAPS MII Eosd GPIOCTL7 TxuneqScrinh INH GPIOCTL3 ADDR=0x00F Gpio 158 Data Bit ADDR=0x00E Gpio 70 Data BitGPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 Txlais TXB1INV TXB2INV TXB3INVADDR=0x09D Transmit AIS, RDI, REI Control Bit Lrdiinh Lreiinh ADDR=0x09F -0x0AE Transmit J0 Bytes 1 Bit TXJ0070ADDR=0x0B0 Transmit K2 Byte Bit ADDR=0x0B3 Transmit S1 Byte Bit TESTS170 Value After ResetADDR=0x0B1 Transmit K1 Byte Bit Preiinh Prdienh Prdiauto Prdi Rxpais Rxuneq Rxplm Auto ENH Rxlop Txpais ADDR=0x0F7 POH Error Generation BitValue 0x18 after Reset ADDR=0x0F8 Transmit C2 Byte Bit Bit name TXC2 W1C J0OOFRxlais Rxlrdi RXK1D K1UNSTAB RXK2D Bit J0OOFD J0OOF delta bit Reserved Dmask Mask RxlaisRXK1D K1UNSTAB RXK2D Rxoofd Rxlofd ADDR=0x0FF Receive TOH Monitor Control Bit Rxlos Rxfram Rxlof Level INH ALGADDR=0x101 Receive Framer Position Control Bit Rxlais Rxlrdi K1UNSTAB S1UNSTAB J0OOF ADDR=0x103 Receive SOH Status Bit RxlosRxoof Rxlof ADDR=0x114 Receive S1 LSBs Bit Bits RXK2 70 APS Signaling The received K2 byteBits 7-0 RXJ0 01570 Section Trace The received 16 J0 bytes ADDR=0x115 Receive K2 Byte Bit Bits B1ERRCNT70 Bits Bits B2ERRCNT70 Bits M1ERRCNT70 ADDR=0x126 Receive Pointer Interpreter Delta Bit ADDR=0x122 Receive Pointer Interpreter Mask BitRxlopd Rxpais Mask Dmask Rxlopd Rxpais Rxlop Rxpais ADDR=0x128 Receive Pointer Status1 BitPSTATE10 ADDR=0x12A Receive Pointer Status2 Bit ADDR=0x12D Receive J1 Reading Control Bit ADDR=0x12E Receive J1 Mode Control BitContent and writes them to RXJ163070 Bit Reserved J1READ ADDR=0x12F Receive RDI Monitor Bit ADDR=0x130 Receive J1 Delta BitJ1AVLD Reserved J1AVL J1OOFD Mask Rxuneq RxplmdMask Dmask ADDR=0x134 -0x173 Receive J1 Bytes Bit ADDR=0x133 Receive J1 OOF BitJ1OOF RXJ1070 RXC2D RXG1D Rxuneq Rxplmd EXPC2 Value After ResetADDR=0x174 Receive Path Delta Bit ADDR=0x176 Expected C2 Byte Bit Rxuneq Rxplm ADDR=0x178 Receive Uneq Monitor BitReserved RXG120 Bits 7-0 B3ERRCNT Bits 7-0 G1ERRCNT 70 The lower byte of the G1 error counter Bits 7-0 G1ERRCNT 158 The upper byte of the G1 error counter Addr = 0x181 Transmit ADR/DPSP Byte Bit Value 0x04 After ResetTxscr Txfcs INH Corr TXADRDPSP70 Value 0x03 after Reset Value 0xDD after Reset MSB Value 0x88 after ResetAddr = 0x185 Transmit Fifo Threshold108 MSB Bit MSBs of the register above Bits Reserved Addr = 0x186 Transmit Laps mode BitTxadr Txcnt Txsapi Txabort Txra INH Txcore Txext Txtype Hdinh HEC Hdrinh Corr Value 0x01 after Reset Value 0xFE after ResetAddr = 0x189 Transmit Sapi MSB Bit Bit name TXSAPIH70 Addr TxmiiframesrecokTxmiialignerr 0x19A Fixed 0x19B Value After Reset Addr = 0x194-0x197 Txer Error CounterAddr = 0x198-0x19B TX Fifo Overflow Error Bit Bit name 0x198 Newtx Fifour Fifoof Ererr Miialign ERR Addr = 0x1A1 Ethernet Transmit Interrupt Mask Bit Newtx Fifour Fifoof Ermask Miialign MaskInterrupt event bit Ethernet Receive Registers Addr = 0x1C0 GFP/LAPS Mode Bit Value 0xA4 after ResetRxdes Rxfcs INH Reminh Addr = 0x1C3 RX Fifo Transmit Threshold108 Bit RXFIFOTHRESHOLD108HIIFGWATERMARK70 Addr = 0x1C5 High Inter-Frame-Gap Water Mark Bit HIIFGWATERMARK108LOIFGWATERMARK70 Addr = 0x1C8 Normal Inter-Frame-Gap Bit Addr = 0x1C7 Low Inter-Frame-Gap Water Mark BitLOIFGWATERMARK108 NORMALIFG40 Bits 7-5 Reserved Reserved LOWIFG40 Value 0x0A After ResetAddr = 0x1C9 Low Inter-Frame-Gap Bit Addr = 0x1CA Receive ADR/TYPEL Bit Bit name Rxadrtypel Addr = 0x1CB Receive Control/TYPEH Bit Bit name Rxcnttypeh Addr = 0x1CD Laps Mode Bit Rxadr Rxcnt Rxsapi Reminh Check INH Addr = 0x1CE GFP Mode Bit Value 0x00 after ResetRxext Addr = 0x1D1 Receive Sapi LSB Bit Bit name RXSAPIL70 Addr = 0x1D0 Receive Pre-Sync States BitRXPRESYNC30 Addr = 0x1D2 Receive Sapi MSB Bit Bit name RXSAPIH70 Rxmiiframesxmitok RX Formdesterr Rxsyncerr Addr = 0x1E8-EB Receive Fifo Underrun Error Addr = 0x1E4-E7 Receive Fifo Overflow Error0x1E6 Fixed 0x1E7 Value After Reset 0x1EA Fixed 0x1EB Value After Reset Addr = 0x1EC Ethernet Receive Interrupt Event Bit ERR W1CCounter Addr = 0x1ED Ethernet Receive Interrupt Mask Bit Newrx Newrx MIN MAX OOS Form Fifour Fifoof Rxmin RXMINSIZE60 Enforce Rxmax Addr = 0x1F4-7 Receive Minimum Frame Size Violations Addr = 0x1F8-B Receive Maximum Frame Size Violations HDMP-3001 LLLLLLLLL-NNN Yyww R.R Ccccc Lllllllll Wafer LOT Number Bottom View of Package Package Dimensions Symbol Min Nom Max Comment Micron CMOS, 1.8V core and 3.3V I/Os Symbol Parameter Units Typ MaxTechnology ESD Power Dissipation DC CharacteristicsAC Electrical Characteristics IL/IIH Prxdmtxd Prxdvmtxen Prxermtxer ↑ Prxclkmtxclk Ptxdmrxd Ptxdvmrxen Ptxermrxer ↑ PtxclkmrxclkPtxdmrxd Ptxdvmrxen Ptxermtxer ↑ Ptxclkmrxclk Timing Diagrams Microprocessor Bus Timing Write Cycle Microprocessor Bus Timing Read Cycle Microprocessor Read Cycle Timing Parameter Description Min ns Max ns Line Interface Receive and Transmit TimingLabel Parameter Min Max Units TOH Interface E1/E2/F1 Transmit Timing Label Parameter Min Typ Max Units TOH Interface E1/E2/F1 Receive Timing DCC Interface Transmit Timing DCC Interface Receive Timing Jtag Interface Timing Reset specification MII Timing MII signal clocking Mode Direction Pin name In/Out Mdio Port Timing Eeprom Port Timing Eeprom Interface Timing Parameters MIN MAX UnitsFrame Declaration 119 120 121 122 Receive Data Link Clock and Data Alignment Applicable Documents