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Agilent Technologies HDMP-3001 manual 120

Models: HDMP-3001

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TX_SONETCLK

TX_FRAME_SFP

TX_E1E2F1_CLK

TX_E1_DATA

E1, F1, E2

APPROX. 750 ns

TX_FRAME_SFP

TX_E1E2F1_CLK

Figure 43. Transmit Overhead Clock and Data Alignment

The transmit overhead clock and data alignment timing diagram (Figure 43) shows the relationship between the TX_E1_DATA, TX_E2_DATA and TX_F1_DATA serial data inputs and their associated clock TX_E1E2F1_CLK. It is a 72 kHz 50% duty cycle clock that is gapped to produce a 64 kHz nominal rate and is aligned as shown.

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Agilent Technologies HDMP-3001 manual 120

Contents

Agilent HDMP-3001 110 116117 118104 105112 113STS-3c/STM-1 Configuration for List of TablesSee the block diagram HDMP-3001 Features ListInternal Functional Blocks Full Duplex Fast EthernetApplications BenefitsInterfaces Data ProcessingPinout Pin AssignmentsReceive Line Alarm Indication Signal Output Receive Loss of Frame OutputContinues Signal name Pin # TypeI/O Signal description Loss of Sonettx clockLoss of Sonetrx clock Received E1/E2/F1 Data Reference Clock a Received Line DCC Data Drop output for receivedTransmit Line DCC Data Input for the Line Data Transmit Section DCC Data Input for the SectionTransmit Section DCC Reference Clock BUS Interface Mode Read Enable Active low Write Enable Active lowSCL SDAGPIO0 GPIO1Dgnd VDDDvdd I/O Buffer Types Buffer types Buffer Type Name CommentPRXDMTXD1 PRXDMTXD2 PRXDMTXD3 Prxdvmtxen Prxermtxer INT TMS, TRSTB, TDIIntroduction Interface Descriptions Microprocessor InterfaceMII Management Interface Eeprom InterfaceInitialization Hardware reset Software ResetSoftware State Machine Reset Bit Order GFP ModeLaps Mode Performance MonitoringTest Loopbacks LoopbacksJtag pins Signal Name Description Interrupt Driven ModePolled Mode JtagApsintb Laps ProcessingFCS Polynomial for Laps Processing Laps ScramblingGFP Processing FCS Polynomial for GFP ProcessingGFP Scrambling SONET/SDH ProcessingIng Overview 3.1 SPE/VC StructureSignal Label C2 3.2 POHPath Trace J1 Path BIP-8 B3Prdiauto Prdienh Rxpais Rxuneq Rxplm RxlopSTS-3c/STM-1 TOH/SOH Row Column Pointer Action Byte H3Section Growth/Spare ZO Section Trace Section BIP-8 B1Line/MS BIP-24 B2 APS Channel and Line/MS AIS/RDI K1 and K2Synchronization Status S1 Line/MS REI M14.2.5 B2 Error Counting 4.1 LOCTransport Overhead Monitoring 4.2.1 J0 MonitoringAPS Monitoring 4.2.10 S1 Monitoring4.2.11 M1 Monitoring Transport Overhead DropPointer Interpretation Current accepted pointer value is incremented by 1 modPointer Processing Path Overhead Monitoring MonitorSupports two methods Pattern Acceptance and Com Path REI Monitoring Path RDI MonitoringSTS-3C/STM-1 Framer Framer Enabled Details Framer Bypass DetailsIf the framer is bypassed Descrambling4.14 B1 Monitor Chip setup and configuration Eeprom Detection Configurations PHY and MAC modeSDH and Sonet mode Laps and GFP modeActive value of 0. Refer to Figure HDMP-3001 Pin Name Microprocessor Pin Name BusmodeWRB WE0 RDB Rdyb Intb Cpuclk ClkoutEeprom Interface Configuration COL VSSRegister Definitions MII Management Register MapBit Type Bit Name Default value Description Chip Register Map SONET/SDH Transmit RegistersAddress Register Name SONET/SDH Transmit Registers SONET/SDH Receive RegistersAddress Register Name Ethernet Transmit RegistersTxsapimsb Ethernet Receive RegistersAddress Register Name State Global CNT Reset Value After ResetLatch ADDR=0x001 Test Modes BitSdapu DISCHIPREV30 PHYADDR40 Rxaps Sumint INTADDR=0x007 Event Summary Bit TohdsumADDR=0x008 Summary Interrupt Mask Bit Apsintb MaskADDR=0x009 Mode of Operation Bit Isolate SONET/SDH PHY/MAC GFP/LAPS MIIADDR=0x00A Rx Event Summary Mask Bit EosdTxuneq Scrinh INHGPIOCTL7 GPIOCTL3ADDR=0x00E Gpio 70 Data Bit GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0ADDR=0x00F Gpio 158 Data Bit GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8TXB1INV TXB2INV TXB3INV ADDR=0x09D Transmit AIS, RDI, REI Control BitTxlais Lrdiinh LreiinhADDR=0x09F -0x0AE Transmit J0 Bytes 1 Bit TXJ0070ADDR=0x0B0 Transmit K2 Byte Bit TESTS170 Value After Reset ADDR=0x0B1 Transmit K1 Byte BitADDR=0x0B3 Transmit S1 Byte Bit Preiinh Prdienh PrdiautoPrdi Rxpais Rxuneq Rxplm Auto ENH RxlopADDR=0x0F7 POH Error Generation Bit Value 0x18 after ResetTxpais ADDR=0x0F8 Transmit C2 Byte Bit Bit name TXC2J0OOF Rxlais Rxlrdi RXK1D K1UNSTAB RXK2DW1C Bit J0OOFD J0OOF delta bit ReservedRxlais RXK1D K1UNSTAB RXK2DDmask Mask Rxoofd RxlofdADDR=0x0FF Receive TOH Monitor Control Bit Rxlos Rxfram Rxlof Level INH ALGADDR=0x101 Receive Framer Position Control Bit Rxlais Rxlrdi K1UNSTAB S1UNSTAB J0OOFADDR=0x103 Receive SOH Status Bit RxlosRxoof Rxlof Bits RXK2 70 APS Signaling The received K2 byte Bits 7-0 RXJ0 01570 Section Trace The received 16 J0 bytesADDR=0x114 Receive S1 LSBs Bit ADDR=0x115 Receive K2 Byte BitBits B1ERRCNT70 BitsBits B2ERRCNT70 Bits M1ERRCNT70 ADDR=0x122 Receive Pointer Interpreter Mask Bit Rxlopd Rxpais Mask DmaskADDR=0x126 Receive Pointer Interpreter Delta Bit Rxlopd RxpaisADDR=0x128 Receive Pointer Status1 Bit PSTATE10Rxlop Rxpais ADDR=0x12A Receive Pointer Status2 BitADDR=0x12E Receive J1 Mode Control Bit Content and writes them to RXJ163070 Bit ReservedADDR=0x12D Receive J1 Reading Control Bit J1READADDR=0x12F Receive RDI Monitor Bit ADDR=0x130 Receive J1 Delta BitJ1AVLD Reserved J1AVL J1OOFD Mask Rxuneq RxplmdMask Dmask ADDR=0x133 Receive J1 OOF Bit J1OOFADDR=0x134 -0x173 Receive J1 Bytes Bit RXJ1070EXPC2 Value After Reset ADDR=0x174 Receive Path Delta BitRXC2D RXG1D Rxuneq Rxplmd ADDR=0x176 Expected C2 Byte BitADDR=0x178 Receive Uneq Monitor Bit Reserved RXG120Rxuneq Rxplm Bits 7-0 B3ERRCNTBits 7-0 G1ERRCNT 70 The lower byte of the G1 error counter Bits 7-0 G1ERRCNT 158 The upper byte of the G1 error counterValue 0x04 After Reset Txscr Txfcs INH CorrAddr = 0x181 Transmit ADR/DPSP Byte Bit TXADRDPSP70Value 0x03 after Reset Value 0xDD after ResetValue 0x88 after Reset Addr = 0x185 Transmit Fifo Threshold108 MSB BitMSB MSBs of the register aboveAddr = 0x186 Transmit Laps mode Bit Txadr Txcnt Txsapi Txabort Txra INHBits Reserved Txcore Txext Txtype Hdinh HEC Hdrinh CorrValue 0x01 after Reset Value 0xFE after ResetAddr = 0x189 Transmit Sapi MSB Bit Bit name TXSAPIH70 Addr TxmiiframesrecokTxmiialignerr Addr = 0x194-0x197 Txer Error Counter Addr = 0x198-0x19B TX Fifo Overflow Error0x19A Fixed 0x19B Value After Reset Bit Bit name 0x198Newtx Fifour Fifoof Ererr Miialign ERR Addr = 0x1A1 Ethernet Transmit Interrupt Mask Bit Newtx Fifour Fifoof Ermask Miialign MaskInterrupt event bit Ethernet Receive Registers Addr = 0x1C0 GFP/LAPS Mode Bit Value 0xA4 after ResetRxdes Rxfcs INH Reminh Addr = 0x1C3 RX Fifo Transmit Threshold108 Bit RXFIFOTHRESHOLD108HIIFGWATERMARK70 Addr = 0x1C5 High Inter-Frame-Gap Water Mark Bit HIIFGWATERMARK108LOIFGWATERMARK70 Addr = 0x1C7 Low Inter-Frame-Gap Water Mark Bit LOIFGWATERMARK108Addr = 0x1C8 Normal Inter-Frame-Gap Bit NORMALIFG40Reserved LOWIFG40 Value 0x0A After Reset Addr = 0x1C9 Low Inter-Frame-Gap BitBits 7-5 Reserved Addr = 0x1CA Receive ADR/TYPEL Bit Bit name RxadrtypelAddr = 0x1CB Receive Control/TYPEH Bit Bit name Rxcnttypeh Addr = 0x1CD Laps Mode Bit Rxadr Rxcnt Rxsapi Reminh Check INHAddr = 0x1CE GFP Mode Bit Value 0x00 after ResetRxext Addr = 0x1D0 Receive Pre-Sync States Bit RXPRESYNC30Addr = 0x1D1 Receive Sapi LSB Bit Bit name RXSAPIL70 Addr = 0x1D2 Receive Sapi MSB Bit Bit name RXSAPIH70Rxmiiframesxmitok RX Formdesterr RxsyncerrAddr = 0x1E4-E7 Receive Fifo Overflow Error 0x1E6 Fixed 0x1E7 Value After ResetAddr = 0x1E8-EB Receive Fifo Underrun Error 0x1EA Fixed 0x1EB Value After ResetAddr = 0x1EC Ethernet Receive Interrupt Event Bit ERR W1CCounter Addr = 0x1ED Ethernet Receive Interrupt Mask Bit Newrx Newrx MIN MAX OOS Form Fifour FifoofRxmin RXMINSIZE60 Enforce RxmaxAddr = 0x1F4-7 Receive Minimum Frame Size Violations Addr = 0x1F8-B Receive Maximum Frame Size ViolationsHDMP-3001 LLLLLLLLL-NNN Yyww R.R Ccccc Lllllllll Wafer LOT NumberBottom View of Package Package Dimensions Symbol Min Nom Max Comment Symbol Parameter Units Typ Max TechnologyMicron CMOS, 1.8V core and 3.3V I/Os ESDDC Characteristics AC Electrical CharacteristicsPower Dissipation IL/IIHPrxdmtxd Prxdvmtxen Prxermtxer ↑ Prxclkmtxclk Ptxdmrxd Ptxdvmrxen Ptxermrxer ↑ PtxclkmrxclkPtxdmrxd Ptxdvmrxen Ptxermtxer ↑ Ptxclkmrxclk Timing Diagrams Microprocessor Bus Timing Write CycleMicroprocessor Bus Timing Read Cycle Microprocessor Read Cycle TimingParameter Description Min ns Max ns Line Interface Receive and Transmit TimingLabel Parameter Min Max Units TOH Interface E1/E2/F1 Transmit Timing Label Parameter Min Typ Max UnitsTOH Interface E1/E2/F1 Receive Timing DCC Interface Transmit TimingDCC Interface Receive Timing Jtag Interface TimingReset specification MII TimingMII signal clocking Mode Direction Pin name In/Out Mdio Port TimingEeprom Port Timing Eeprom Interface Timing Parameters MIN MAX UnitsFrame Declaration 119 120 121 122 Receive Data Link Clock and Data Alignment Applicable Documents