4.14 B1 Monitor | Agilent Technologies HDMP-3001 specification

3.9.4.14 B1 Monitor

In both modes, the HDMP-3001 checks the received B1 bytes for correct Bit Interleaved Parity 8 (BIP-8) values. Even parity BIP-8 is calculated over all bytes of each frame before descrambling. This value is then compared to the re- ceived B1 value in the following frame after descrambling. The comparison can result in 0 to 8 mismatches (B1 bit errors).

The HDMP-3001 contains a 16-bit B1 error counter that counts ev- ery B1 bit error. When the performance monitoring counters are latched (LATCH_EVENT tran- sitions high), the value of this counter is latched to the

B1_ERRCNT[15:0] register, and the B1 error counter is cleared.

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Agilent Technologies HDMP-3001 manual 4.14 B1 Monitor

HDMP-3001 specifications

Agilent Technologies, a prominent name in electronics and measurement technology, offers a wide range of products that cater to various industries. Among its notable offerings is the HDMP-3001, a high-speed, serial data transceiver designed to facilitate robust communications in electronic systems. The HDMP-3001 stands out with its ability to handle high bandwidths, making it particularly suited for applications requiring rapid data transfer, such as telecommunications, computer networking, and high-performance computing.

One of the main features of the HDMP-3001 is its advanced signaling technology. By employing differential signaling, the transceiver minimizes electromagnetic interference and enhances signal integrity. This is crucial in environments with multiple electronic devices operating simultaneously, as it ensures data is transmitted clearly and without degradation.

The HDMP-3001 operates at a maximum data rate of 1 Gbps, allowing for efficient data transfer over short distances. This capability is coupled with a flexible architecture that enables users to configure the transceiver for various applications. The device supports both point-to-point and point-to-multipoint configurations, giving engineers the versatility they need in designing communication links.

Moreover, the HDMP-3001 features on-chip clock recovery functionality, which simplifies system design by reducing the number of external components needed. This built-in feature allows the transceiver to maintain synchronization even as data rates increase, further enhancing performance.

The low power consumption characteristic of the HDMP-3001 is another notable advantage. This makes it an attractive choice for battery-operated devices and systems where power efficiency is critical. The transceiver’s design ensures optimal performance while minimizing heat generation and power draw, enabling longer operational lifetimes.

In terms of physical characteristics, the HDMP-3001 comes in a compact, surface-mount package, allowing for easier integration into various circuit board designs. The small form factor, combined with its innovative technology, makes it a popular choice among engineers seeking to improve data transmission reliability without compromising on space or power constraints.

Overall, Agilent Technologies' HDMP-3001 is a formidable solution for high-speed serial data transmission, characterized by its robust performance, low power consumption, and versatile configuration options. With these features, it continues to be an essential component in the evolving landscape of electronic communications.

Contents

Agilent HDMP-3001 116 110117 118 105 104112 113 List of Tables STS-3c/STM-1 Configuration for HDMP-3001 Features List See the block diagramInternal Functional Blocks Full Duplex Fast Ethernet Benefits ApplicationsInterfaces Data Processing Pin Assignments Pinout Receive Loss of Frame Output Receive Line Alarm Indication Signal OutputContinues Loss of Sonettx clock Signal name Pin # TypeI/O Signal descriptionLoss of Sonetrx clock Received Line DCC Data Drop output for received Received E1/E2/F1 Data Reference Clock a Transmit Section DCC Data Input for the Section Transmit Line DCC Data Input for the Line DataTransmit Section DCC Reference Clock BUS Interface Mode Write Enable Active low Read Enable Active low SDA SCLGPIO0 GPIO1 VDD DgndDvdd Buffer types Buffer Type Name Comment I/O Buffer TypesPRXDMTXD1 PRXDMTXD2 PRXDMTXD3 Prxdvmtxen Prxermtxer INT TMS, TRSTB, TDI Interface Descriptions Microprocessor Interface IntroductionMII Management Interface Eeprom Interface Software Reset Initialization Hardware resetSoftware State Machine Reset Bit Order GFP Mode Performance Monitoring Laps Mode Loopbacks Test Loopbacks Interrupt Driven Mode Jtag pins Signal Name DescriptionPolled Mode Jtag Laps Processing Apsintb Laps Scrambling FCS Polynomial for Laps ProcessingGFP Processing FCS Polynomial for GFP Processing SONET/SDH Processing GFP Scrambling 3.1 SPE/VC Structure Ing Overview 3.2 POH Signal Label C2Path Trace J1 Path BIP-8 B3 Rxlop Prdiauto Prdienh Rxpais Rxuneq Rxplm Pointer Action Byte H3 STS-3c/STM-1 TOH/SOH Row ColumnSection Growth/Spare ZO Section Trace Section BIP-8 B1 APS Channel and Line/MS AIS/RDI K1 and K2 Line/MS BIP-24 B2Synchronization Status S1 Line/MS REI M1 4.1 LOC 4.2.5 B2 Error CountingTransport Overhead Monitoring 4.2.1 J0 Monitoring 4.2.10 S1 Monitoring APS Monitoring4.2.11 M1 Monitoring Transport Overhead Drop Current accepted pointer value is incremented by 1 mod Pointer InterpretationPointer Processing Monitor Path Overhead MonitoringSupports two methods Pattern Acceptance and Com Path RDI Monitoring Path REI MonitoringSTS-3C/STM-1 Framer Framer Bypass Details Framer Enabled DetailsIf the framer is bypassed Descrambling 4.14 B1 Monitor Configurations PHY and MAC mode Chip setup and configuration Eeprom DetectionSDH and Sonet mode Laps and GFP mode Active value of 0. Refer to Figure Busmode HDMP-3001 Pin Name Microprocessor Pin NameWRB WE0 RDB Rdyb Intb Cpuclk Clkout COL VSS Eeprom Interface Configuration MII Management Register Map Register Definitions Bit Type Bit Name Default value Description SONET/SDH Transmit Registers Chip Register Map SONET/SDH Receive Registers Address Register Name SONET/SDH Transmit Registers Ethernet Transmit Registers Address Register Name Ethernet Receive Registers Txsapimsb Address Register Name Value After Reset State Global CNT ResetLatch ADDR=0x001 Test Modes Bit DIS SdapuCHIPREV30 Rxaps Sumint INT PHYADDR40 Tohdsum ADDR=0x007 Event Summary BitADDR=0x008 Summary Interrupt Mask Bit Apsintb Mask Isolate SONET/SDH PHY/MAC GFP/LAPS MII ADDR=0x009 Mode of Operation BitADDR=0x00A Rx Event Summary Mask Bit Eosd Scrinh INH TxuneqGPIOCTL7 GPIOCTL3 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 ADDR=0x00E Gpio 70 Data BitADDR=0x00F Gpio 158 Data Bit GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 ADDR=0x09D Transmit AIS, RDI, REI Control Bit TXB1INV TXB2INV TXB3INVTxlais Lrdiinh Lreiinh TXJ0070 ADDR=0x09F -0x0AE Transmit J0 Bytes 1 BitADDR=0x0B0 Transmit K2 Byte Bit ADDR=0x0B1 Transmit K1 Byte Bit TESTS170 Value After ResetADDR=0x0B3 Transmit S1 Byte Bit Preiinh Prdienh Prdiauto Auto ENH Rxlop Prdi Rxpais Rxuneq Rxplm Value 0x18 after Reset ADDR=0x0F7 POH Error Generation BitTxpais ADDR=0x0F8 Transmit C2 Byte Bit Bit name TXC2 Rxlais Rxlrdi RXK1D K1UNSTAB RXK2D J0OOFW1C Bit J0OOFD J0OOF delta bit Reserved RXK1D K1UNSTAB RXK2D RxlaisDmask Mask Rxoofd Rxlofd Rxlos Rxfram Rxlof Level INH ALG ADDR=0x0FF Receive TOH Monitor Control BitADDR=0x101 Receive Framer Position Control Bit K1UNSTAB S1UNSTAB J0OOF Rxlais Rxlrdi Rxlos ADDR=0x103 Receive SOH Status BitRxoof Rxlof Bits 7-0 RXJ0 01570 Section Trace The received 16 J0 bytes Bits RXK2 70 APS Signaling The received K2 byteADDR=0x114 Receive S1 LSBs Bit ADDR=0x115 Receive K2 Byte Bit Bits Bits B1ERRCNT70 Bits B2ERRCNT70 Bits M1ERRCNT70 Rxlopd Rxpais Mask Dmask ADDR=0x122 Receive Pointer Interpreter Mask BitADDR=0x126 Receive Pointer Interpreter Delta Bit Rxlopd Rxpais PSTATE10 ADDR=0x128 Receive Pointer Status1 BitRxlop Rxpais ADDR=0x12A Receive Pointer Status2 Bit Content and writes them to RXJ163070 Bit Reserved ADDR=0x12E Receive J1 Mode Control BitADDR=0x12D Receive J1 Reading Control Bit J1READ ADDR=0x130 Receive J1 Delta Bit ADDR=0x12F Receive RDI Monitor BitJ1AVLD Reserved Rxuneq Rxplmd J1AVL J1OOFD MaskMask Dmask J1OOF ADDR=0x133 Receive J1 OOF BitADDR=0x134 -0x173 Receive J1 Bytes Bit RXJ1070 ADDR=0x174 Receive Path Delta Bit EXPC2 Value After ResetRXC2D RXG1D Rxuneq Rxplmd ADDR=0x176 Expected C2 Byte Bit Reserved RXG120 ADDR=0x178 Receive Uneq Monitor BitRxuneq Rxplm Bits 7-0 B3ERRCNT Bits 7-0 G1ERRCNT 158 The upper byte of the G1 error counter Bits 7-0 G1ERRCNT 70 The lower byte of the G1 error counter Txscr Txfcs INH Corr Value 0x04 After ResetAddr = 0x181 Transmit ADR/DPSP Byte Bit TXADRDPSP70 Value 0xDD after Reset Value 0x03 after Reset Addr = 0x185 Transmit Fifo Threshold108 MSB Bit Value 0x88 after ResetMSB MSBs of the register above Txadr Txcnt Txsapi Txabort Txra INH Addr = 0x186 Transmit Laps mode BitBits Reserved Txcore Txext Txtype Hdinh HEC Hdrinh Corr Value 0xFE after Reset Value 0x01 after ResetAddr = 0x189 Transmit Sapi MSB Bit Bit name TXSAPIH70 Txmiiframesrecok AddrTxmiialignerr Addr = 0x198-0x19B TX Fifo Overflow Error Addr = 0x194-0x197 Txer Error Counter0x19A Fixed 0x19B Value After Reset Bit Bit name 0x198 Newtx Fifour Fifoof Ererr Miialign ERR Newtx Fifour Fifoof Ermask Miialign Mask Addr = 0x1A1 Ethernet Transmit Interrupt Mask BitInterrupt event bit Value 0xA4 after Reset Ethernet Receive Registers Addr = 0x1C0 GFP/LAPS Mode BitRxdes Rxfcs INH Reminh RXFIFOTHRESHOLD108 Addr = 0x1C3 RX Fifo Transmit Threshold108 BitHIIFGWATERMARK70 HIIFGWATERMARK108 Addr = 0x1C5 High Inter-Frame-Gap Water Mark BitLOIFGWATERMARK70 LOIFGWATERMARK108 Addr = 0x1C7 Low Inter-Frame-Gap Water Mark BitAddr = 0x1C8 Normal Inter-Frame-Gap Bit NORMALIFG40 Addr = 0x1C9 Low Inter-Frame-Gap Bit Reserved LOWIFG40 Value 0x0A After ResetBits 7-5 Reserved Addr = 0x1CA Receive ADR/TYPEL Bit Bit name Rxadrtypel Addr = 0x1CB Receive Control/TYPEH Bit Bit name Rxcnttypeh Rxadr Rxcnt Rxsapi Reminh Check INH Addr = 0x1CD Laps Mode Bit Value 0x00 after Reset Addr = 0x1CE GFP Mode BitRxext RXPRESYNC30 Addr = 0x1D0 Receive Pre-Sync States BitAddr = 0x1D1 Receive Sapi LSB Bit Bit name RXSAPIL70 Addr = 0x1D2 Receive Sapi MSB Bit Bit name RXSAPIH70 Rxmiiframesxmitok Rxsyncerr RX Formdesterr 0x1E6 Fixed 0x1E7 Value After Reset Addr = 0x1E4-E7 Receive Fifo Overflow ErrorAddr = 0x1E8-EB Receive Fifo Underrun Error 0x1EA Fixed 0x1EB Value After Reset ERR W1C Addr = 0x1EC Ethernet Receive Interrupt Event BitCounter Newrx Newrx MIN MAX OOS Form Fifour Fifoof Addr = 0x1ED Ethernet Receive Interrupt Mask Bit Rxmax Rxmin RXMINSIZE60 Enforce Addr = 0x1F8-B Receive Maximum Frame Size Violations Addr = 0x1F4-7 Receive Minimum Frame Size Violations LLLLLLLLL-NNN Yyww R.R Ccccc Lllllllll Wafer LOT Number HDMP-3001 Bottom View of Package Package Dimensions Symbol Min Nom Max Comment Technology Symbol Parameter Units Typ MaxMicron CMOS, 1.8V core and 3.3V I/Os ESD AC Electrical Characteristics DC CharacteristicsPower Dissipation IL/IIH Ptxdmrxd Ptxdvmrxen Ptxermrxer ↑ Ptxclkmrxclk Prxdmtxd Prxdvmtxen Prxermtxer ↑ PrxclkmtxclkPtxdmrxd Ptxdvmrxen Ptxermtxer ↑ Ptxclkmrxclk Microprocessor Bus Timing Write Cycle Timing Diagrams Microprocessor Read Cycle Timing Microprocessor Bus Timing Read Cycle Line Interface Receive and Transmit Timing Parameter Description Min ns Max nsLabel Parameter Min Max Units Label Parameter Min Typ Max Units TOH Interface E1/E2/F1 Transmit Timing DCC Interface Transmit Timing TOH Interface E1/E2/F1 Receive Timing Jtag Interface Timing DCC Interface Receive Timing MII Timing Reset specification Mdio Port Timing MII signal clocking Mode Direction Pin name In/Out MIN MAX Units Eeprom Port Timing Eeprom Interface Timing ParametersFrame Declaration 119 120 121 122 Receive Data Link Clock and Data Alignment Applicable Documents