packet. When this occurs an interrupt is generated. The packet can be ended via generation of an FCS error, via an abort sequence, or via “fill” bytes inserted in the gap, depending upon a software configurable escape code.

•Maintains performance monitor counters.

3.8.1.1FCS Polynomial for LAPS Processing

The HDMP-3001 supports CRC-32 Frame Check Sequence (FCS) generation and checking. The polynomial used to generate and

check the FCS is

X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1.

The FCS field is calculated over all bits of the Address, Control, Payload, Information and Padding fields, not including any octets inserted for transparency. This does not include the Flag Se- quences nor the FCS field itself.

The CRC generator and checker are initialized to all ones. Upon completion of the FCS calculation the FCS value is ones-comple- mented. It is this new value that is inserted in the FCS field.

3.8.1.2LAPS Scrambling

Scrambling is performed to pro- tect the SONET/SDH line against malicious users deliberately send- ing packets to cause long run-lengths of ones or zeros or replicating the SONET/SDH fram- ing bytes. In the transmit direction an X43 +1 scrambler scrambles all SPE payload data. In the receive direction, a self-syn- chronous X43 +1 descrambler recovers the scrambled data.

3.8.2 GFP Processing

The Transmit GFP Processor pro- vides the insertion of packet- based information into the STS SPE. It provides packet encapsu- lation, FCS field generation, inter-packet fill and scrambling. The GFP Processor performs the following functions:

•Counts the Ethernet frame length.

•Calculates the payload length field, (PLI).

•Performs XOR with values as shown in Figure 11.

•Generates and sends cHEC and XOR (Figure 11).

•Sends programmable TYPE values.

•Generates and sends tHEC.

•Sends programmable DP, SP, and SPARE.

•Generates and sends eHEC.

•Generates and sends optional FCS.

3.8.2.1FCS Polynomial for GFP Processing

The HDMP-3001 supports CRC-32 Frame Check Sequence (FCS) generation and checking. The polynomial used to generate and

check the FCS is

X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1.

The FCS field is calculated over the GFP payload, excluding all headers. The CRC generator and checker are initialized to all ones. Upon completion of the FCS cal- culation the FCS value is ones-complemented. It is this new value that is inserted in the FCS field.

3.8.2.2HEC Polynomial for GFP Processing

The following polynomial is used for generating and checking the

HECs:

X16 + X12 + X5 + 1

An HEC is calculated over each header. The initial value of the CRC registers is zero and the HEC is not inverted before being sent.

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Agilent Technologies HDMP-3001 manual FCS Polynomial for Laps Processing, Laps Scrambling, GFP Processing
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HDMP-3001 specifications

Agilent Technologies, a prominent name in electronics and measurement technology, offers a wide range of products that cater to various industries. Among its notable offerings is the HDMP-3001, a high-speed, serial data transceiver designed to facilitate robust communications in electronic systems. The HDMP-3001 stands out with its ability to handle high bandwidths, making it particularly suited for applications requiring rapid data transfer, such as telecommunications, computer networking, and high-performance computing.

One of the main features of the HDMP-3001 is its advanced signaling technology. By employing differential signaling, the transceiver minimizes electromagnetic interference and enhances signal integrity. This is crucial in environments with multiple electronic devices operating simultaneously, as it ensures data is transmitted clearly and without degradation.

The HDMP-3001 operates at a maximum data rate of 1 Gbps, allowing for efficient data transfer over short distances. This capability is coupled with a flexible architecture that enables users to configure the transceiver for various applications. The device supports both point-to-point and point-to-multipoint configurations, giving engineers the versatility they need in designing communication links.

Moreover, the HDMP-3001 features on-chip clock recovery functionality, which simplifies system design by reducing the number of external components needed. This built-in feature allows the transceiver to maintain synchronization even as data rates increase, further enhancing performance.

The low power consumption characteristic of the HDMP-3001 is another notable advantage. This makes it an attractive choice for battery-operated devices and systems where power efficiency is critical. The transceiver’s design ensures optimal performance while minimizing heat generation and power draw, enabling longer operational lifetimes.

In terms of physical characteristics, the HDMP-3001 comes in a compact, surface-mount package, allowing for easier integration into various circuit board designs. The small form factor, combined with its innovative technology, makes it a popular choice among engineers seeking to improve data transmission reliability without compromising on space or power constraints.

Overall, Agilent Technologies' HDMP-3001 is a formidable solution for high-speed serial data transmission, characterized by its robust performance, low power consumption, and versatile configuration options. With these features, it continues to be an essential component in the evolving landscape of electronic communications.
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