scrambles the entire SONET/SDH frame except for the first row of TOH/SOH. For testing purposes, the scrambler can be disabled through the SCR_INH bit in the register map.

3.9.4Receive SONET/SDH Processing Details

3.9.4.1 LOC

The RX_SONETCLK input is monitored for loss of clock using the TCLK input. If no transitions are detected on RX_SONETCLK for 24 periods of the 25 MHz sys- tem clock, the RX_LOC pin is set. It is cleared when transitions are again detected.

3.9.4.2Transport Overhead Monitoring

The TOH/SOH monitoring block consists of J0, B2, K1, K2, S1 and M1 monitoring. These TOH/SOH bytes are monitored for errors or changes in states.

3.9.4.2.1 J0 Monitoring

There are two modes of operation for J0 monitoring, one typically used in SONET applications, the other used in SDH applications. In SONET mode, J0 monitoring con- sists of examining the received J0 bytes for values that match con- sistently for three consecutive frames. When a consistent J0 value is received, it is written to RX_J0[15]_[7:0].

In SDH mode, the J0 byte is ex- pected to contain a repeating

16-byte section trace frame that includes the Section Access Point Identifier. J0 monitoring consists of locking on to the start of the

16-byte section trace frame and examining the received section trace frames for values that match consistently for three consecutive section trace frames. When a con-

sistent frame value is received, it is written to RX_J0[15:0]_[7:0]. The first byte of the section trace frame (which contains the frame start marker) is written to RX_J0[15]_[7:0].

3.9.4.2.2 Framing

The MSBs of all section trace frame bytes are zero, except for the MSB of the frame start marker byte. The J0 monitor framer searches for 15 consecutive J0 bytes that have a zero in their MSB, followed by a J0 byte with a one in its MSB. When this pat- tern is found, the framer goes into frame mode, J0_OOF = 0. Once the J0 monitor framer is in frame, it remains in frame until three consecutive section trace frames are received with at least one MSB bit error. In SONET mode, the J0 frame indication is held in the in-frame state, J0_OOF = 0. The J0_OOF_D delta bit is set when J0_OOF changes state.

3.9.4.2.3Pattern Acceptance and Comparison

Once in frame, the J0 monitor block looks for three consecutive 16 byte (SDH mode) or one byte (SONET) section trace frames. When three consecutive identical frames are received, the accepted frame is stored in RX_J0[15:0]_[7:0] (or RX_J0[15]_[7:0] in the SONET mode).

3.9.4.2.4BIP-24 (B2) Checking

The HDMP-3001 checks the re- ceived B2 bytes for correct BIP-8 values. (The 3 B2 bytes together form a BIP-24.) Even parity BIP- 24 is calculated over all groups of three bytes of each frame, except the first three rows of TOH (SOH in SONET and RSOH in SDH). The calculation is done on the re- ceived data after descrambling.

This value is then compared to the B2 values in the following frame after descrambling. The comparison can result in from 0 to 24 mismatches (B2 bit errors). The number of B2 bit errors de- tected each frame is inserted into the transmitted M1 TOH byte.

3.9.4.2.5 B2 Error Counting

The HDMP-3001 contains a 20-bit B2 error counter that counts ev- ery B2 bit error. When the performance monitoring counters are latched (LATCH_EVENT tran- sitions high), the value of this counter is latched to the

B2_ERRCNT[23:0] register, and the B2 error counter is cleared.

3.9.4.2.6 K1K2 Monitoring

The K1 and K2 bytes, which are used for sending Line/MS AIS or RDI and for APS signaling, are monitored for change in status.

3.9.4.2.7Line/MS AIS Monitoring and LRDI Generation

The three LSBs of K2 can be used as a AIS or Remote Defect Indica- tion (RDI) at the line/MS level. If they are received as 111 for

K2_CONSEC[3:0] consecutive frames, RX_LAIS is set, and the RX_LAIS_OUT output is high. If for K2_CONSEC[3:0] consecutive frames, they are not received as 111, then RX_LAIS and RX_LAIS_OUT are cleared. The RX_LAIS_D delta bit is set when RX_LAIS changes state.

3.9.4.2.8Line/MS RDI Monitoring

The three LSBs of K2 are also monitored for K2_CONSEC[3:0] consecutive receptions or non- receptions of 110. When this is received, RX_LRDI is set or cleared. RX_LRDI_D is set when RX_LRDI changes state.

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Agilent Technologies HDMP-3001 4.1 LOC, Transport Overhead Monitoring, 4.2.1 J0 Monitoring, Framing, BIP-24 B2 Checking
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HDMP-3001 specifications

Agilent Technologies, a prominent name in electronics and measurement technology, offers a wide range of products that cater to various industries. Among its notable offerings is the HDMP-3001, a high-speed, serial data transceiver designed to facilitate robust communications in electronic systems. The HDMP-3001 stands out with its ability to handle high bandwidths, making it particularly suited for applications requiring rapid data transfer, such as telecommunications, computer networking, and high-performance computing.

One of the main features of the HDMP-3001 is its advanced signaling technology. By employing differential signaling, the transceiver minimizes electromagnetic interference and enhances signal integrity. This is crucial in environments with multiple electronic devices operating simultaneously, as it ensures data is transmitted clearly and without degradation.

The HDMP-3001 operates at a maximum data rate of 1 Gbps, allowing for efficient data transfer over short distances. This capability is coupled with a flexible architecture that enables users to configure the transceiver for various applications. The device supports both point-to-point and point-to-multipoint configurations, giving engineers the versatility they need in designing communication links.

Moreover, the HDMP-3001 features on-chip clock recovery functionality, which simplifies system design by reducing the number of external components needed. This built-in feature allows the transceiver to maintain synchronization even as data rates increase, further enhancing performance.

The low power consumption characteristic of the HDMP-3001 is another notable advantage. This makes it an attractive choice for battery-operated devices and systems where power efficiency is critical. The transceiver’s design ensures optimal performance while minimizing heat generation and power draw, enabling longer operational lifetimes.

In terms of physical characteristics, the HDMP-3001 comes in a compact, surface-mount package, allowing for easier integration into various circuit board designs. The small form factor, combined with its innovative technology, makes it a popular choice among engineers seeking to improve data transmission reliability without compromising on space or power constraints.

Overall, Agilent Technologies' HDMP-3001 is a formidable solution for high-speed serial data transmission, characterized by its robust performance, low power consumption, and versatile configuration options. With these features, it continues to be an essential component in the evolving landscape of electronic communications.
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