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Agilent Technologies HDMP-3001 manual Value 0x01 after Reset, Value 0xFE after Reset

Models: HDMP-3001

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ADDR = 0x188: Transmit SAPI LSB / Spare Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit name TX_SAPI_L_SPARE[7:0]

R/W R/W

Value 0x01 after

reset

Bits 7-0: TX_SAPI_L_SPARE[7:0] is the LSB of the SAPI field in LAPS mode and the spare field byte in GFP frame. In LAPS mode it is sent as part of the header unless the TX_SAPI_INH bit is set. In GFP mode it is part of the extended header and is sent if TX_EXT_HDR_INH is not set.

ADDR = 0x189: Transmit SAPI MSB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit name TX_SAPI_H[7:0]

R/W R/W

Value 0xFE after

reset

Bits 7-0: TX_SAPI_H[7:0] is the MSB of the SAPI field in the LAPS header. It is inhibited by the TX_SAPI_INH bit.

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Agilent Technologies HDMP-3001 manual Value 0x01 after Reset, Addr = 0x189 Transmit Sapi MSB Bit Bit name TXSAPIH70

HDMP-3001 specifications

Agilent Technologies, a prominent name in electronics and measurement technology, offers a wide range of products that cater to various industries. Among its notable offerings is the HDMP-3001, a high-speed, serial data transceiver designed to facilitate robust communications in electronic systems. The HDMP-3001 stands out with its ability to handle high bandwidths, making it particularly suited for applications requiring rapid data transfer, such as telecommunications, computer networking, and high-performance computing.

One of the main features of the HDMP-3001 is its advanced signaling technology. By employing differential signaling, the transceiver minimizes electromagnetic interference and enhances signal integrity. This is crucial in environments with multiple electronic devices operating simultaneously, as it ensures data is transmitted clearly and without degradation.

The HDMP-3001 operates at a maximum data rate of 1 Gbps, allowing for efficient data transfer over short distances. This capability is coupled with a flexible architecture that enables users to configure the transceiver for various applications. The device supports both point-to-point and point-to-multipoint configurations, giving engineers the versatility they need in designing communication links.

Moreover, the HDMP-3001 features on-chip clock recovery functionality, which simplifies system design by reducing the number of external components needed. This built-in feature allows the transceiver to maintain synchronization even as data rates increase, further enhancing performance.

The low power consumption characteristic of the HDMP-3001 is another notable advantage. This makes it an attractive choice for battery-operated devices and systems where power efficiency is critical. The transceiver’s design ensures optimal performance while minimizing heat generation and power draw, enabling longer operational lifetimes.

In terms of physical characteristics, the HDMP-3001 comes in a compact, surface-mount package, allowing for easier integration into various circuit board designs. The small form factor, combined with its innovative technology, makes it a popular choice among engineers seeking to improve data transmission reliability without compromising on space or power constraints.

Overall, Agilent Technologies' HDMP-3001 is a formidable solution for high-speed serial data transmission, characterized by its robust performance, low power consumption, and versatile configuration options. With these features, it continues to be an essential component in the evolving landscape of electronic communications.

Contents

Agilent HDMP-3001 118 110116 117113 104105 112List of Tables STS-3c/STM-1 Configuration forFull Duplex Fast Ethernet See the block diagramHDMP-3001 Features List Internal Functional BlocksData Processing ApplicationsBenefits InterfacesPin Assignments PinoutContinues Receive Line Alarm Indication Signal OutputReceive Loss of Frame Output Loss of Sonetrx clock Signal name Pin # TypeI/O Signal descriptionLoss of Sonettx clock Received Line DCC Data Drop output for received Received E1/E2/F1 Data Reference Clock aTransmit Section DCC Reference Clock Transmit Line DCC Data Input for the Line DataTransmit Section DCC Data Input for the Section BUS Interface Mode Write Enable Active low Read Enable Active lowGPIO1 SCLSDA GPIO0Dvdd DgndVDD TMS, TRSTB, TDI I/O Buffer TypesBuffer types Buffer Type Name Comment PRXDMTXD1 PRXDMTXD2 PRXDMTXD3 Prxdvmtxen Prxermtxer INTEeprom Interface IntroductionInterface Descriptions Microprocessor Interface MII Management InterfaceBit Order GFP Mode Initialization Hardware resetSoftware Reset Software State Machine ResetPerformance Monitoring Laps ModeLoopbacks Test LoopbacksJtag Jtag pins Signal Name DescriptionInterrupt Driven Mode Polled ModeLaps Processing ApsintbFCS Polynomial for GFP Processing FCS Polynomial for Laps ProcessingLaps Scrambling GFP ProcessingSONET/SDH Processing GFP Scrambling3.1 SPE/VC Structure Ing OverviewPath BIP-8 B3 Signal Label C23.2 POH Path Trace J1Rxlop Prdiauto Prdienh Rxpais Rxuneq RxplmSection BIP-8 B1 STS-3c/STM-1 TOH/SOH Row ColumnPointer Action Byte H3 Section Growth/Spare ZO Section TraceLine/MS REI M1 Line/MS BIP-24 B2APS Channel and Line/MS AIS/RDI K1 and K2 Synchronization Status S14.2.1 J0 Monitoring 4.2.5 B2 Error Counting4.1 LOC Transport Overhead MonitoringTransport Overhead Drop APS Monitoring4.2.10 S1 Monitoring 4.2.11 M1 MonitoringPointer Processing Pointer InterpretationCurrent accepted pointer value is incremented by 1 mod Supports two methods Path Overhead MonitoringMonitor Pattern Acceptance and Com STS-3C/STM-1 Framer Path REI MonitoringPath RDI Monitoring Descrambling Framer Enabled DetailsFramer Bypass Details If the framer is bypassed4.14 B1 Monitor Laps and GFP mode Chip setup and configuration Eeprom DetectionConfigurations PHY and MAC mode SDH and Sonet modeActive value of 0. Refer to Figure Cpuclk Clkout HDMP-3001 Pin Name Microprocessor Pin NameBusmode WRB WE0 RDB Rdyb IntbCOL VSS Eeprom Interface ConfigurationMII Management Register Map Register DefinitionsBit Type Bit Name Default value Description SONET/SDH Transmit Registers Chip Register MapSONET/SDH Receive Registers Address Register Name SONET/SDH Transmit RegistersEthernet Transmit Registers Address Register NameEthernet Receive Registers TxsapimsbAddress Register Name ADDR=0x001 Test Modes Bit State Global CNT ResetValue After Reset LatchCHIPREV30 SdapuDIS Rxaps Sumint INT PHYADDR40Apsintb Mask ADDR=0x007 Event Summary BitTohdsum ADDR=0x008 Summary Interrupt Mask BitEosd ADDR=0x009 Mode of Operation BitIsolate SONET/SDH PHY/MAC GFP/LAPS MII ADDR=0x00A Rx Event Summary Mask BitGPIOCTL3 TxuneqScrinh INH GPIOCTL7GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 ADDR=0x00E Gpio 70 Data BitGPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 ADDR=0x00F Gpio 158 Data BitLrdiinh Lreiinh TXB1INV TXB2INV TXB3INVADDR=0x09D Transmit AIS, RDI, REI Control Bit TxlaisADDR=0x0B0 Transmit K2 Byte Bit ADDR=0x09F -0x0AE Transmit J0 Bytes 1 BitTXJ0070 Preiinh Prdienh Prdiauto TESTS170 Value After ResetADDR=0x0B1 Transmit K1 Byte Bit ADDR=0x0B3 Transmit S1 Byte BitAuto ENH Rxlop Prdi Rxpais Rxuneq RxplmADDR=0x0F8 Transmit C2 Byte Bit Bit name TXC2 ADDR=0x0F7 POH Error Generation BitValue 0x18 after Reset TxpaisBit J0OOFD J0OOF delta bit Reserved J0OOFRxlais Rxlrdi RXK1D K1UNSTAB RXK2D W1CRxoofd Rxlofd RxlaisRXK1D K1UNSTAB RXK2D Dmask MaskADDR=0x101 Receive Framer Position Control Bit ADDR=0x0FF Receive TOH Monitor Control BitRxlos Rxfram Rxlof Level INH ALG K1UNSTAB S1UNSTAB J0OOF Rxlais RxlrdiRxoof Rxlof ADDR=0x103 Receive SOH Status BitRxlos ADDR=0x115 Receive K2 Byte Bit Bits RXK2 70 APS Signaling The received K2 byteBits 7-0 RXJ0 01570 Section Trace The received 16 J0 bytes ADDR=0x114 Receive S1 LSBs BitBits Bits B1ERRCNT70Bits B2ERRCNT70 Bits M1ERRCNT70 Rxlopd Rxpais ADDR=0x122 Receive Pointer Interpreter Mask BitRxlopd Rxpais Mask Dmask ADDR=0x126 Receive Pointer Interpreter Delta BitADDR=0x12A Receive Pointer Status2 Bit ADDR=0x128 Receive Pointer Status1 BitPSTATE10 Rxlop RxpaisJ1READ ADDR=0x12E Receive J1 Mode Control BitContent and writes them to RXJ163070 Bit Reserved ADDR=0x12D Receive J1 Reading Control BitJ1AVLD Reserved ADDR=0x12F Receive RDI Monitor BitADDR=0x130 Receive J1 Delta Bit Mask Dmask J1AVL J1OOFD MaskRxuneq Rxplmd RXJ1070 ADDR=0x133 Receive J1 OOF BitJ1OOF ADDR=0x134 -0x173 Receive J1 Bytes BitADDR=0x176 Expected C2 Byte Bit EXPC2 Value After ResetADDR=0x174 Receive Path Delta Bit RXC2D RXG1D Rxuneq RxplmdBits 7-0 B3ERRCNT ADDR=0x178 Receive Uneq Monitor BitReserved RXG120 Rxuneq RxplmBits 7-0 G1ERRCNT 158 The upper byte of the G1 error counter Bits 7-0 G1ERRCNT 70 The lower byte of the G1 error counterTXADRDPSP70 Value 0x04 After ResetTxscr Txfcs INH Corr Addr = 0x181 Transmit ADR/DPSP Byte BitValue 0xDD after Reset Value 0x03 after ResetMSBs of the register above Value 0x88 after ResetAddr = 0x185 Transmit Fifo Threshold108 MSB Bit MSBTxcore Txext Txtype Hdinh HEC Hdrinh Corr Addr = 0x186 Transmit Laps mode BitTxadr Txcnt Txsapi Txabort Txra INH Bits ReservedAddr = 0x189 Transmit Sapi MSB Bit Bit name TXSAPIH70 Value 0x01 after ResetValue 0xFE after Reset Txmiialignerr AddrTxmiiframesrecok Bit Bit name 0x198 Addr = 0x194-0x197 Txer Error CounterAddr = 0x198-0x19B TX Fifo Overflow Error 0x19A Fixed 0x19B Value After ResetNewtx Fifour Fifoof Ererr Miialign ERR Interrupt event bit Addr = 0x1A1 Ethernet Transmit Interrupt Mask BitNewtx Fifour Fifoof Ermask Miialign Mask Rxdes Rxfcs INH Reminh Ethernet Receive Registers Addr = 0x1C0 GFP/LAPS Mode BitValue 0xA4 after Reset HIIFGWATERMARK70 Addr = 0x1C3 RX Fifo Transmit Threshold108 BitRXFIFOTHRESHOLD108 LOIFGWATERMARK70 Addr = 0x1C5 High Inter-Frame-Gap Water Mark BitHIIFGWATERMARK108 NORMALIFG40 Addr = 0x1C7 Low Inter-Frame-Gap Water Mark BitLOIFGWATERMARK108 Addr = 0x1C8 Normal Inter-Frame-Gap BitAddr = 0x1CA Receive ADR/TYPEL Bit Bit name Rxadrtypel Reserved LOWIFG40 Value 0x0A After ResetAddr = 0x1C9 Low Inter-Frame-Gap Bit Bits 7-5 ReservedAddr = 0x1CB Receive Control/TYPEH Bit Bit name Rxcnttypeh Rxadr Rxcnt Rxsapi Reminh Check INH Addr = 0x1CD Laps Mode BitRxext Addr = 0x1CE GFP Mode BitValue 0x00 after Reset Addr = 0x1D2 Receive Sapi MSB Bit Bit name RXSAPIH70 Addr = 0x1D0 Receive Pre-Sync States BitRXPRESYNC30 Addr = 0x1D1 Receive Sapi LSB Bit Bit name RXSAPIL70Rxmiiframesxmitok Rxsyncerr RX Formdesterr0x1EA Fixed 0x1EB Value After Reset Addr = 0x1E4-E7 Receive Fifo Overflow Error0x1E6 Fixed 0x1E7 Value After Reset Addr = 0x1E8-EB Receive Fifo Underrun ErrorCounter Addr = 0x1EC Ethernet Receive Interrupt Event BitERR W1C Newrx Newrx MIN MAX OOS Form Fifour Fifoof Addr = 0x1ED Ethernet Receive Interrupt Mask BitRxmax Rxmin RXMINSIZE60 EnforceAddr = 0x1F8-B Receive Maximum Frame Size Violations Addr = 0x1F4-7 Receive Minimum Frame Size ViolationsLLLLLLLLL-NNN Yyww R.R Ccccc Lllllllll Wafer LOT Number HDMP-3001Bottom View of Package Package Dimensions Symbol Min Nom Max Comment ESD Symbol Parameter Units Typ MaxTechnology Micron CMOS, 1.8V core and 3.3V I/OsIL/IIH DC CharacteristicsAC Electrical Characteristics Power DissipationPtxdmrxd Ptxdvmrxen Ptxermtxer ↑ Ptxclkmrxclk Prxdmtxd Prxdvmtxen Prxermtxer ↑ PrxclkmtxclkPtxdmrxd Ptxdvmrxen Ptxermrxer ↑ Ptxclkmrxclk Microprocessor Bus Timing Write Cycle Timing DiagramsMicroprocessor Read Cycle Timing Microprocessor Bus Timing Read CycleLabel Parameter Min Max Units Parameter Description Min ns Max nsLine Interface Receive and Transmit Timing Label Parameter Min Typ Max Units TOH Interface E1/E2/F1 Transmit TimingDCC Interface Transmit Timing TOH Interface E1/E2/F1 Receive TimingJtag Interface Timing DCC Interface Receive TimingMII Timing Reset specificationMdio Port Timing MII signal clocking Mode Direction Pin name In/OutFrame Declaration Eeprom Port Timing Eeprom Interface Timing ParametersMIN MAX Units 119 120 121 122 Receive Data Link Clock and Data Alignment Applicable Documents