Manuals / Agilent Technologies / TV and Video / CRT Television

Agilent Technologies HDMP-3001 manual Prxdmtxd Prxdvmtxen Prxermtxer ↑ Prxclkmtxclk

Models: HDMP-3001

1 124

Download 124 pages 6.83 Kb

Page 109

Image 109

7.5.2 MII specifications

Table 29. MII AC Specification

Parameter	Min	Max	Units	Conditions

PHY mode output Setup time	10		ns
P_RXD_M_TXD,
P_RX_DV_M_TX_EN,
P_RX_ER_M_TX_ER,
↑ P_RX_CLK_M_TX_CLK

PHY mode output hold time	10		ns
P_RXD_M_TXD,
P_RX_DV_M_TX_EN,
P_RX_ER_M_TX_ER,
↑ P_RX_CLK_M_TX_CLK

MAC mode output Setup time	15		ns
P_RXD_M_TXD,
P_RX_DV_M_TX_EN,
P_RX_ER_M_TX_ER,
↑ P_RX_CLK_M_TX_CLK

MAC mode output hold time	0		ns
P_RXD_M_TXD,
P_RX_DV_M_TX_EN,
P_RX_ER_M_TX_ER,
↑ P_RX_CLK_M_TX_CLK

PHY mode Input Setup time	15		ns
P_TXD_M_RXD,
P_TX_DV_M_RX_EN,
P_TX_ER_M_RX_ER,
↑ P_TX_CLK_M_RX_CLK

PHY mode Input hold time	0		ns
P_TXD_M_RXD,
P_TX_DV_M_RX_EN,
P_TX_ER_M_TX_ER,
↑ P_TX_CLK_M_RX_CLK

MAC mode Input Setup time	10		ns
P_TXD_M_RXD,
P_TX_DV_M_RX_EN,
P_TX_ER_M_TX_ER,
↑ P_TX_CLK_M_RX_CLK

MAC mode Input hold time	10		ns
P_TXD_M_RXD,
P_TX_DV_M_RX_EN,

P_TX_ER_M_TX_ER,

↑ P_TX_CLK_M_RX_CLK

109

Page 109

Image 109

Agilent Technologies HDMP-3001 manual Prxdmtxd Prxdvmtxen Prxermtxer ↑ Prxclkmtxclk

Contents

Agilent HDMP-3001 116 110117 118105 104112 113List of Tables STS-3c/STM-1 Configuration forHDMP-3001 Features List See the block diagramInternal Functional Blocks Full Duplex Fast EthernetBenefits ApplicationsInterfaces Data ProcessingPin Assignments PinoutReceive Loss of Frame Output Receive Line Alarm Indication Signal OutputContinues Loss of Sonettx clock Signal name Pin # TypeI/O Signal descriptionLoss of Sonetrx clock Received Line DCC Data Drop output for received Received E1/E2/F1 Data Reference Clock aTransmit Section DCC Data Input for the Section Transmit Line DCC Data Input for the Line DataTransmit Section DCC Reference Clock BUS Interface Mode Write Enable Active low Read Enable Active lowSDA SCLGPIO0 GPIO1VDD DgndDvdd Buffer types Buffer Type Name Comment I/O Buffer TypesPRXDMTXD1 PRXDMTXD2 PRXDMTXD3 Prxdvmtxen Prxermtxer INT TMS, TRSTB, TDIInterface Descriptions Microprocessor Interface IntroductionMII Management Interface Eeprom InterfaceSoftware Reset Initialization Hardware resetSoftware State Machine Reset Bit Order GFP ModePerformance Monitoring Laps ModeLoopbacks Test LoopbacksInterrupt Driven Mode Jtag pins Signal Name DescriptionPolled Mode JtagLaps Processing ApsintbLaps Scrambling FCS Polynomial for Laps ProcessingGFP Processing FCS Polynomial for GFP ProcessingSONET/SDH Processing GFP Scrambling3.1 SPE/VC Structure Ing Overview3.2 POH Signal Label C2Path Trace J1 Path BIP-8 B3Rxlop Prdiauto Prdienh Rxpais Rxuneq RxplmPointer Action Byte H3 STS-3c/STM-1 TOH/SOH Row ColumnSection Growth/Spare ZO Section Trace Section BIP-8 B1APS Channel and Line/MS AIS/RDI K1 and K2 Line/MS BIP-24 B2Synchronization Status S1 Line/MS REI M14.1 LOC 4.2.5 B2 Error CountingTransport Overhead Monitoring 4.2.1 J0 Monitoring4.2.10 S1 Monitoring APS Monitoring4.2.11 M1 Monitoring Transport Overhead DropCurrent accepted pointer value is incremented by 1 mod Pointer InterpretationPointer Processing Monitor Path Overhead MonitoringSupports two methods Pattern Acceptance and Com Path RDI Monitoring Path REI MonitoringSTS-3C/STM-1 Framer Framer Bypass Details Framer Enabled DetailsIf the framer is bypassed Descrambling4.14 B1 Monitor Configurations PHY and MAC mode Chip setup and configuration Eeprom DetectionSDH and Sonet mode Laps and GFP modeActive value of 0. Refer to Figure Busmode HDMP-3001 Pin Name Microprocessor Pin NameWRB WE0 RDB Rdyb Intb Cpuclk ClkoutCOL VSS Eeprom Interface ConfigurationMII Management Register Map Register DefinitionsBit Type Bit Name Default value Description SONET/SDH Transmit Registers Chip Register MapSONET/SDH Receive Registers Address Register Name SONET/SDH Transmit RegistersEthernet Transmit Registers Address Register NameEthernet Receive Registers TxsapimsbAddress Register Name Value After Reset State Global CNT ResetLatch ADDR=0x001 Test Modes BitDIS SdapuCHIPREV30 Rxaps Sumint INT PHYADDR40Tohdsum ADDR=0x007 Event Summary BitADDR=0x008 Summary Interrupt Mask Bit Apsintb MaskIsolate SONET/SDH PHY/MAC GFP/LAPS MII ADDR=0x009 Mode of Operation BitADDR=0x00A Rx Event Summary Mask Bit EosdScrinh INH TxuneqGPIOCTL7 GPIOCTL3GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 ADDR=0x00E Gpio 70 Data BitADDR=0x00F Gpio 158 Data Bit GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8ADDR=0x09D Transmit AIS, RDI, REI Control Bit TXB1INV TXB2INV TXB3INVTxlais Lrdiinh LreiinhTXJ0070 ADDR=0x09F -0x0AE Transmit J0 Bytes 1 BitADDR=0x0B0 Transmit K2 Byte Bit ADDR=0x0B1 Transmit K1 Byte Bit TESTS170 Value After ResetADDR=0x0B3 Transmit S1 Byte Bit Preiinh Prdienh PrdiautoAuto ENH Rxlop Prdi Rxpais Rxuneq RxplmValue 0x18 after Reset ADDR=0x0F7 POH Error Generation BitTxpais ADDR=0x0F8 Transmit C2 Byte Bit Bit name TXC2Rxlais Rxlrdi RXK1D K1UNSTAB RXK2D J0OOFW1C Bit J0OOFD J0OOF delta bit ReservedRXK1D K1UNSTAB RXK2D RxlaisDmask Mask Rxoofd RxlofdRxlos Rxfram Rxlof Level INH ALG ADDR=0x0FF Receive TOH Monitor Control BitADDR=0x101 Receive Framer Position Control Bit K1UNSTAB S1UNSTAB J0OOF Rxlais RxlrdiRxlos ADDR=0x103 Receive SOH Status BitRxoof Rxlof Bits 7-0 RXJ0 01570 Section Trace The received 16 J0 bytes Bits RXK2 70 APS Signaling The received K2 byteADDR=0x114 Receive S1 LSBs Bit ADDR=0x115 Receive K2 Byte BitBits Bits B1ERRCNT70Bits B2ERRCNT70 Bits M1ERRCNT70 Rxlopd Rxpais Mask Dmask ADDR=0x122 Receive Pointer Interpreter Mask BitADDR=0x126 Receive Pointer Interpreter Delta Bit Rxlopd RxpaisPSTATE10 ADDR=0x128 Receive Pointer Status1 BitRxlop Rxpais ADDR=0x12A Receive Pointer Status2 BitContent and writes them to RXJ163070 Bit Reserved ADDR=0x12E Receive J1 Mode Control BitADDR=0x12D Receive J1 Reading Control Bit J1READADDR=0x130 Receive J1 Delta Bit ADDR=0x12F Receive RDI Monitor BitJ1AVLD Reserved Rxuneq Rxplmd J1AVL J1OOFD MaskMask Dmask J1OOF ADDR=0x133 Receive J1 OOF BitADDR=0x134 -0x173 Receive J1 Bytes Bit RXJ1070ADDR=0x174 Receive Path Delta Bit EXPC2 Value After ResetRXC2D RXG1D Rxuneq Rxplmd ADDR=0x176 Expected C2 Byte BitReserved RXG120 ADDR=0x178 Receive Uneq Monitor BitRxuneq Rxplm Bits 7-0 B3ERRCNTBits 7-0 G1ERRCNT 158 The upper byte of the G1 error counter Bits 7-0 G1ERRCNT 70 The lower byte of the G1 error counterTxscr Txfcs INH Corr Value 0x04 After ResetAddr = 0x181 Transmit ADR/DPSP Byte Bit TXADRDPSP70Value 0xDD after Reset Value 0x03 after ResetAddr = 0x185 Transmit Fifo Threshold108 MSB Bit Value 0x88 after ResetMSB MSBs of the register aboveTxadr Txcnt Txsapi Txabort Txra INH Addr = 0x186 Transmit Laps mode BitBits Reserved Txcore Txext Txtype Hdinh HEC Hdrinh CorrValue 0xFE after Reset Value 0x01 after ResetAddr = 0x189 Transmit Sapi MSB Bit Bit name TXSAPIH70 Txmiiframesrecok AddrTxmiialignerr Addr = 0x198-0x19B TX Fifo Overflow Error Addr = 0x194-0x197 Txer Error Counter0x19A Fixed 0x19B Value After Reset Bit Bit name 0x198Newtx Fifour Fifoof Ererr Miialign ERR Newtx Fifour Fifoof Ermask Miialign Mask Addr = 0x1A1 Ethernet Transmit Interrupt Mask BitInterrupt event bit Value 0xA4 after Reset Ethernet Receive Registers Addr = 0x1C0 GFP/LAPS Mode BitRxdes Rxfcs INH Reminh RXFIFOTHRESHOLD108 Addr = 0x1C3 RX Fifo Transmit Threshold108 BitHIIFGWATERMARK70 HIIFGWATERMARK108 Addr = 0x1C5 High Inter-Frame-Gap Water Mark BitLOIFGWATERMARK70 LOIFGWATERMARK108 Addr = 0x1C7 Low Inter-Frame-Gap Water Mark BitAddr = 0x1C8 Normal Inter-Frame-Gap Bit NORMALIFG40Addr = 0x1C9 Low Inter-Frame-Gap Bit Reserved LOWIFG40 Value 0x0A After ResetBits 7-5 Reserved Addr = 0x1CA Receive ADR/TYPEL Bit Bit name RxadrtypelAddr = 0x1CB Receive Control/TYPEH Bit Bit name Rxcnttypeh Rxadr Rxcnt Rxsapi Reminh Check INH Addr = 0x1CD Laps Mode BitValue 0x00 after Reset Addr = 0x1CE GFP Mode BitRxext RXPRESYNC30 Addr = 0x1D0 Receive Pre-Sync States BitAddr = 0x1D1 Receive Sapi LSB Bit Bit name RXSAPIL70 Addr = 0x1D2 Receive Sapi MSB Bit Bit name RXSAPIH70Rxmiiframesxmitok Rxsyncerr RX Formdesterr0x1E6 Fixed 0x1E7 Value After Reset Addr = 0x1E4-E7 Receive Fifo Overflow ErrorAddr = 0x1E8-EB Receive Fifo Underrun Error 0x1EA Fixed 0x1EB Value After ResetERR W1C Addr = 0x1EC Ethernet Receive Interrupt Event BitCounter Newrx Newrx MIN MAX OOS Form Fifour Fifoof Addr = 0x1ED Ethernet Receive Interrupt Mask BitRxmax Rxmin RXMINSIZE60 EnforceAddr = 0x1F8-B Receive Maximum Frame Size Violations Addr = 0x1F4-7 Receive Minimum Frame Size ViolationsLLLLLLLLL-NNN Yyww R.R Ccccc Lllllllll Wafer LOT Number HDMP-3001Bottom View of Package Package Dimensions Symbol Min Nom Max Comment Technology Symbol Parameter Units Typ MaxMicron CMOS, 1.8V core and 3.3V I/Os ESDAC Electrical Characteristics DC CharacteristicsPower Dissipation IL/IIHPtxdmrxd Ptxdvmrxen Ptxermrxer ↑ Ptxclkmrxclk Prxdmtxd Prxdvmtxen Prxermtxer ↑ PrxclkmtxclkPtxdmrxd Ptxdvmrxen Ptxermtxer ↑ Ptxclkmrxclk Microprocessor Bus Timing Write Cycle Timing DiagramsMicroprocessor Read Cycle Timing Microprocessor Bus Timing Read CycleLine Interface Receive and Transmit Timing Parameter Description Min ns Max nsLabel Parameter Min Max Units Label Parameter Min Typ Max Units TOH Interface E1/E2/F1 Transmit TimingDCC Interface Transmit Timing TOH Interface E1/E2/F1 Receive TimingJtag Interface Timing DCC Interface Receive TimingMII Timing Reset specificationMdio Port Timing MII signal clocking Mode Direction Pin name In/OutMIN MAX Units Eeprom Port Timing Eeprom Interface Timing ParametersFrame Declaration 119 120 121 122 Receive Data Link Clock and Data Alignment Applicable Documents

P_RXD_M_TXD,

P_RX_DV_M_TX_EN,

P_RX_ER_M_TX_ER,

↑ P_RX_CLK_M_TX_CLK

P_TXD_M_RXD,

P_TX_DV_M_RX_EN,

P_TX_ER_M_RX_ER,

↑ P_TX_CLK_M_RX_CLK

P_TXD_M_RXD,

P_TX_DV_M_RX_EN,

P_TX_ER_M_TX_ER,

↑ P_TX_CLK_M_RX_CLK