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Agilent Technologies HDMP-3001 manual Timing Diagrams, Microprocessor Bus Timing Write Cycle

Models: HDMP-3001

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8. Timing Diagrams

8.1 Microprocessor Bus Timing - Write Cycle

INPUTS

OUTPUTS

BIDIR

	t2
	t6
A[8:0]	VALID
CSB
WRB
RDB
D[7:0] (IN)	VALID
	VALID

Hi - Z

D[7:0] (OUT)

Hi - Z

RDYB*

GPIO[15:0]

NEW VALUE

Figure 29. Microprocessor Write Cycle Timing.

*RDYB is re-clocked twice by the microprocessor clock in addition to the timing shown. This adds an additional delay of between one and two microprocessor clock cycles.

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Page 110

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Agilent Technologies HDMP-3001 manual Timing Diagrams, Microprocessor Bus Timing Write Cycle

Contents

Agilent HDMP-3001 117 110116 118112 104105 113STS-3c/STM-1 Configuration for List of TablesInternal Functional Blocks See the block diagramHDMP-3001 Features List Full Duplex Fast EthernetInterfaces ApplicationsBenefits Data ProcessingPinout Pin AssignmentsContinues Receive Line Alarm Indication Signal OutputReceive Loss of Frame Output Loss of Sonetrx clock Signal name Pin # TypeI/O Signal descriptionLoss of Sonettx clock Received E1/E2/F1 Data Reference Clock a Received Line DCC Data Drop output for receivedTransmit Section DCC Reference Clock Transmit Line DCC Data Input for the Line DataTransmit Section DCC Data Input for the Section BUS Interface Mode Read Enable Active low Write Enable Active lowGPIO0 SCLSDA GPIO1Dvdd DgndVDD PRXDMTXD1 PRXDMTXD2 PRXDMTXD3 Prxdvmtxen Prxermtxer INT I/O Buffer TypesBuffer types Buffer Type Name Comment TMS, TRSTB, TDIMII Management Interface IntroductionInterface Descriptions Microprocessor Interface Eeprom InterfaceSoftware State Machine Reset Initialization Hardware resetSoftware Reset Bit Order GFP ModeLaps Mode Performance MonitoringTest Loopbacks LoopbacksPolled Mode Jtag pins Signal Name DescriptionInterrupt Driven Mode JtagApsintb Laps ProcessingGFP Processing FCS Polynomial for Laps ProcessingLaps Scrambling FCS Polynomial for GFP ProcessingGFP Scrambling SONET/SDH ProcessingIng Overview 3.1 SPE/VC StructurePath Trace J1 Signal Label C23.2 POH Path BIP-8 B3Prdiauto Prdienh Rxpais Rxuneq Rxplm RxlopSection Growth/Spare ZO Section Trace STS-3c/STM-1 TOH/SOH Row ColumnPointer Action Byte H3 Section BIP-8 B1Synchronization Status S1 Line/MS BIP-24 B2APS Channel and Line/MS AIS/RDI K1 and K2 Line/MS REI M1Transport Overhead Monitoring 4.2.5 B2 Error Counting4.1 LOC 4.2.1 J0 Monitoring4.2.11 M1 Monitoring APS Monitoring4.2.10 S1 Monitoring Transport Overhead DropPointer Processing Pointer InterpretationCurrent accepted pointer value is incremented by 1 mod Supports two methods Path Overhead MonitoringMonitor Pattern Acceptance and Com STS-3C/STM-1 Framer Path REI MonitoringPath RDI Monitoring If the framer is bypassed Framer Enabled DetailsFramer Bypass Details Descrambling4.14 B1 Monitor SDH and Sonet mode Chip setup and configuration Eeprom DetectionConfigurations PHY and MAC mode Laps and GFP modeActive value of 0. Refer to Figure WRB WE0 RDB Rdyb Intb HDMP-3001 Pin Name Microprocessor Pin NameBusmode Cpuclk ClkoutEeprom Interface Configuration COL VSSRegister Definitions MII Management Register MapBit Type Bit Name Default value Description Chip Register Map SONET/SDH Transmit RegistersAddress Register Name SONET/SDH Transmit Registers SONET/SDH Receive RegistersAddress Register Name Ethernet Transmit RegistersTxsapimsb Ethernet Receive RegistersAddress Register Name Latch State Global CNT ResetValue After Reset ADDR=0x001 Test Modes BitCHIPREV30 SdapuDIS PHYADDR40 Rxaps Sumint INTADDR=0x008 Summary Interrupt Mask Bit ADDR=0x007 Event Summary BitTohdsum Apsintb MaskADDR=0x00A Rx Event Summary Mask Bit ADDR=0x009 Mode of Operation BitIsolate SONET/SDH PHY/MAC GFP/LAPS MII EosdGPIOCTL7 TxuneqScrinh INH GPIOCTL3ADDR=0x00F Gpio 158 Data Bit ADDR=0x00E Gpio 70 Data BitGPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8Txlais TXB1INV TXB2INV TXB3INVADDR=0x09D Transmit AIS, RDI, REI Control Bit Lrdiinh LreiinhADDR=0x0B0 Transmit K2 Byte Bit ADDR=0x09F -0x0AE Transmit J0 Bytes 1 BitTXJ0070 ADDR=0x0B3 Transmit S1 Byte Bit TESTS170 Value After ResetADDR=0x0B1 Transmit K1 Byte Bit Preiinh Prdienh PrdiautoPrdi Rxpais Rxuneq Rxplm Auto ENH RxlopTxpais ADDR=0x0F7 POH Error Generation BitValue 0x18 after Reset ADDR=0x0F8 Transmit C2 Byte Bit Bit name TXC2W1C J0OOFRxlais Rxlrdi RXK1D K1UNSTAB RXK2D Bit J0OOFD J0OOF delta bit ReservedDmask Mask RxlaisRXK1D K1UNSTAB RXK2D Rxoofd RxlofdADDR=0x101 Receive Framer Position Control Bit ADDR=0x0FF Receive TOH Monitor Control BitRxlos Rxfram Rxlof Level INH ALG Rxlais Rxlrdi K1UNSTAB S1UNSTAB J0OOFRxoof Rxlof ADDR=0x103 Receive SOH Status BitRxlos ADDR=0x114 Receive S1 LSBs Bit Bits RXK2 70 APS Signaling The received K2 byteBits 7-0 RXJ0 01570 Section Trace The received 16 J0 bytes ADDR=0x115 Receive K2 Byte BitBits B1ERRCNT70 BitsBits B2ERRCNT70 Bits M1ERRCNT70 ADDR=0x126 Receive Pointer Interpreter Delta Bit ADDR=0x122 Receive Pointer Interpreter Mask BitRxlopd Rxpais Mask Dmask Rxlopd RxpaisRxlop Rxpais ADDR=0x128 Receive Pointer Status1 BitPSTATE10 ADDR=0x12A Receive Pointer Status2 BitADDR=0x12D Receive J1 Reading Control Bit ADDR=0x12E Receive J1 Mode Control BitContent and writes them to RXJ163070 Bit Reserved J1READJ1AVLD Reserved ADDR=0x12F Receive RDI Monitor BitADDR=0x130 Receive J1 Delta Bit Mask Dmask J1AVL J1OOFD MaskRxuneq Rxplmd ADDR=0x134 -0x173 Receive J1 Bytes Bit ADDR=0x133 Receive J1 OOF BitJ1OOF RXJ1070RXC2D RXG1D Rxuneq Rxplmd EXPC2 Value After ResetADDR=0x174 Receive Path Delta Bit ADDR=0x176 Expected C2 Byte BitRxuneq Rxplm ADDR=0x178 Receive Uneq Monitor BitReserved RXG120 Bits 7-0 B3ERRCNTBits 7-0 G1ERRCNT 70 The lower byte of the G1 error counter Bits 7-0 G1ERRCNT 158 The upper byte of the G1 error counterAddr = 0x181 Transmit ADR/DPSP Byte Bit Value 0x04 After ResetTxscr Txfcs INH Corr TXADRDPSP70Value 0x03 after Reset Value 0xDD after ResetMSB Value 0x88 after ResetAddr = 0x185 Transmit Fifo Threshold108 MSB Bit MSBs of the register aboveBits Reserved Addr = 0x186 Transmit Laps mode BitTxadr Txcnt Txsapi Txabort Txra INH Txcore Txext Txtype Hdinh HEC Hdrinh CorrAddr = 0x189 Transmit Sapi MSB Bit Bit name TXSAPIH70 Value 0x01 after ResetValue 0xFE after Reset Txmiialignerr AddrTxmiiframesrecok 0x19A Fixed 0x19B Value After Reset Addr = 0x194-0x197 Txer Error CounterAddr = 0x198-0x19B TX Fifo Overflow Error Bit Bit name 0x198Newtx Fifour Fifoof Ererr Miialign ERR Interrupt event bit Addr = 0x1A1 Ethernet Transmit Interrupt Mask BitNewtx Fifour Fifoof Ermask Miialign Mask Rxdes Rxfcs INH Reminh Ethernet Receive Registers Addr = 0x1C0 GFP/LAPS Mode BitValue 0xA4 after Reset HIIFGWATERMARK70 Addr = 0x1C3 RX Fifo Transmit Threshold108 BitRXFIFOTHRESHOLD108 LOIFGWATERMARK70 Addr = 0x1C5 High Inter-Frame-Gap Water Mark BitHIIFGWATERMARK108 Addr = 0x1C8 Normal Inter-Frame-Gap Bit Addr = 0x1C7 Low Inter-Frame-Gap Water Mark BitLOIFGWATERMARK108 NORMALIFG40Bits 7-5 Reserved Reserved LOWIFG40 Value 0x0A After ResetAddr = 0x1C9 Low Inter-Frame-Gap Bit Addr = 0x1CA Receive ADR/TYPEL Bit Bit name RxadrtypelAddr = 0x1CB Receive Control/TYPEH Bit Bit name Rxcnttypeh Addr = 0x1CD Laps Mode Bit Rxadr Rxcnt Rxsapi Reminh Check INHRxext Addr = 0x1CE GFP Mode BitValue 0x00 after Reset Addr = 0x1D1 Receive Sapi LSB Bit Bit name RXSAPIL70 Addr = 0x1D0 Receive Pre-Sync States BitRXPRESYNC30 Addr = 0x1D2 Receive Sapi MSB Bit Bit name RXSAPIH70Rxmiiframesxmitok RX Formdesterr RxsyncerrAddr = 0x1E8-EB Receive Fifo Underrun Error Addr = 0x1E4-E7 Receive Fifo Overflow Error0x1E6 Fixed 0x1E7 Value After Reset 0x1EA Fixed 0x1EB Value After ResetCounter Addr = 0x1EC Ethernet Receive Interrupt Event BitERR W1C Addr = 0x1ED Ethernet Receive Interrupt Mask Bit Newrx Newrx MIN MAX OOS Form Fifour FifoofRxmin RXMINSIZE60 Enforce RxmaxAddr = 0x1F4-7 Receive Minimum Frame Size Violations Addr = 0x1F8-B Receive Maximum Frame Size ViolationsHDMP-3001 LLLLLLLLL-NNN Yyww R.R Ccccc Lllllllll Wafer LOT NumberBottom View of Package Package Dimensions Symbol Min Nom Max Comment Micron CMOS, 1.8V core and 3.3V I/Os Symbol Parameter Units Typ MaxTechnology ESDPower Dissipation DC CharacteristicsAC Electrical Characteristics IL/IIHPtxdmrxd Ptxdvmrxen Ptxermtxer ↑ Ptxclkmrxclk Prxdmtxd Prxdvmtxen Prxermtxer ↑ PrxclkmtxclkPtxdmrxd Ptxdvmrxen Ptxermrxer ↑ Ptxclkmrxclk Timing Diagrams Microprocessor Bus Timing Write CycleMicroprocessor Bus Timing Read Cycle Microprocessor Read Cycle TimingLabel Parameter Min Max Units Parameter Description Min ns Max nsLine Interface Receive and Transmit Timing TOH Interface E1/E2/F1 Transmit Timing Label Parameter Min Typ Max UnitsTOH Interface E1/E2/F1 Receive Timing DCC Interface Transmit TimingDCC Interface Receive Timing Jtag Interface TimingReset specification MII TimingMII signal clocking Mode Direction Pin name In/Out Mdio Port TimingFrame Declaration Eeprom Port Timing Eeprom Interface Timing ParametersMIN MAX Units 119 120 121 122 Receive Data Link Clock and Data Alignment Applicable Documents