Agilent Technologies HDMP-3001 Parameter Description Min ns Max ns, Label Parameter Min Max Units

8.3Microprocessor Bus Timing Table Table 30. Timing of microprocessor bus

Parameter		Description	Min (ns)	Max (ns)
t1		CS_N active to RDYB driven to inactive state	0	15
t2		CS_N, WRB and RDB valid to A and D captured	90	270
t	3	1CS_N, WRB and RDB valid to RDYB active	1401	2201
t4		BUSMODE 0: WRB inactive to RDYB inactive	0	15
		BUSMODE 1: RDB inactive to RDYB inactive
t5		CS_N inactive to RDYB in high impedance state	0	15
t6		CS_N, WRB and RDB valid to GPIO outputs updated (when the	250	370
		GPIOs are the target of the write cycle)
t7		CS_N, WRB and RDB valid to A captured	90	270
t8		CS_N, WRB and RDB valid to GPIO inputs captured (when the	300	520
		GPIOs are the target of the read cycle)
t9		CS_N, WRB and RDB valid to D valid	600	750
t10		1D valid to RDYB active	501	601
t11		CS_N, WRB and RDB valid to RDYB active	650	850
t12		RDB inactive to D in high impedance state	0	15

Note 1: RDYB is re-clocked twice by the microprocessor clock in addition to the timing shown. This adds an additional delay of between one and two microprocessor clock cycles.

8.4 Line Interface Receive and Transmit Timing

TX_SONETCLK tVTDFC

tHTDFC

TX_DATA[7:0]

tHFOFC

TX_FRAME_SFP

tVFOFC

Figure 31. Line Interface Transmit Timing

Label	Parameter	Min	Max	Units
TX_SONETCLK	TX_SONETCLK frequency	19.44-20ppm	19.44+20ppm	MHz
tHTDFC	TX_DATA hold time	1		ns
tVTDFC	TX_DATA transition from TX_CLK high		15	ns
tHFOFC	TX_FRAME_SFP hold time	1		ns
tVFOFC	TX_FRAME_SFP transition from TX_CLK high		15	ns

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