Agilent Technologies HDMP-3001 manual Addr = 0x186 Transmit Laps mode Bit, Bits Reserved

Models: HDMP-3001

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ADDR = 0x186: Transmit LAPS mode

 

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit name

Reserved

Reserved

Reserved

TX_ADR_

TX_CNT_ TX_SAPI_

TX_ABORT

TX_RA_

 

 

 

 

INH

INH

INH

_INH

INH

 

 

 

 

 

 

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

Value

0

0

0

0

0

0

0

0

after

 

 

 

 

 

 

 

 

reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits 7-5:

Reserved

 

 

 

 

 

 

 

Bit 4:

TX_ADR_INH is set to inhibit the insertion of the programmed address byte into the LAPS frame

 

for test purposes. Instead, the byte is taken from the MII payload.

 

 

Bit 3: TX_CNT_INH is set to inhibit the insertion of the programmed control byte into the LAPS frame for test purposes. Instead, the byte is taken from the MII payload.

Bit 2: TX_SAPI_INH is set to inhibit the insertion of the two programmed SAPI bytes into the LAPS frame for test purposes. Instead, the bytes are taken from the MII payload.

Bit 1: TX_ABORT_INH is set to inhibit the generation of abort sequence in case an error condition occurs during Ethernet TX processing.

Bit 0:

TX_RA_INH is set to inhibit the generation of the rate adaptation sequence when an underrun

 

occurs in the TX FIFO. If the abort sequence is also inhibited, the FCS is corrupted.

 

ADDR = 0x187: Transmit GFP Mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

 

 

 

 

 

 

 

 

 

Bit name

Reserved

Reserved

Reserved

TX_CORE

TX_EXT_

TX_EXT_

TX_TYPE_

TX_TYPE_

 

 

 

 

_HD_INH

HEC_

HDR_INH

HEC_

HDR_INH

 

 

 

 

 

CORR

 

CORR

 

 

 

 

 

 

 

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

Value

0

0

0

0

0

0

0

0

after

 

 

 

 

 

 

 

 

reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits 7-5:

Reserved

 

 

 

 

 

 

 

Bit 4:

TX_CORE_HD_INH inhibits the insertion of a core header in the payload for test purposes. Idle

 

packet core headers are always enabled. A state machine reset is required to make changes to

 

this bit effective. When active, the Type and Extended headers should also be inhibited.

Bit 3: TX_EXT_HEC_CORR corrupts the extended header HEC.

Bit 2: TX_EXT_HDR_INH is set to inhibit the generation of the GFP Frame Payload Extended Header, which includes the {DP,SP} byte, Spare byte, and LSB and MSB bytes of eHEC. This bit is set to create a GFP null header.

Bit 1: TX_TYPE_HEC_CORR corrupts the type header HEC.

Bit 0: TX_TYPE_HDR_INH is set to inhibit the insertion of the programmed Type Header and tHEC bytes for test purposes. Instead, the four bytes are taken from the MII payload.

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Agilent Technologies HDMP-3001 Addr = 0x186 Transmit Laps mode Bit, Txadr Txcnt Txsapi Txabort Txra INH, Bits Reserved

HDMP-3001 specifications

Agilent Technologies, a prominent name in electronics and measurement technology, offers a wide range of products that cater to various industries. Among its notable offerings is the HDMP-3001, a high-speed, serial data transceiver designed to facilitate robust communications in electronic systems. The HDMP-3001 stands out with its ability to handle high bandwidths, making it particularly suited for applications requiring rapid data transfer, such as telecommunications, computer networking, and high-performance computing.

One of the main features of the HDMP-3001 is its advanced signaling technology. By employing differential signaling, the transceiver minimizes electromagnetic interference and enhances signal integrity. This is crucial in environments with multiple electronic devices operating simultaneously, as it ensures data is transmitted clearly and without degradation.

The HDMP-3001 operates at a maximum data rate of 1 Gbps, allowing for efficient data transfer over short distances. This capability is coupled with a flexible architecture that enables users to configure the transceiver for various applications. The device supports both point-to-point and point-to-multipoint configurations, giving engineers the versatility they need in designing communication links.

Moreover, the HDMP-3001 features on-chip clock recovery functionality, which simplifies system design by reducing the number of external components needed. This built-in feature allows the transceiver to maintain synchronization even as data rates increase, further enhancing performance.

The low power consumption characteristic of the HDMP-3001 is another notable advantage. This makes it an attractive choice for battery-operated devices and systems where power efficiency is critical. The transceiver’s design ensures optimal performance while minimizing heat generation and power draw, enabling longer operational lifetimes.

In terms of physical characteristics, the HDMP-3001 comes in a compact, surface-mount package, allowing for easier integration into various circuit board designs. The small form factor, combined with its innovative technology, makes it a popular choice among engineers seeking to improve data transmission reliability without compromising on space or power constraints.

Overall, Agilent Technologies' HDMP-3001 is a formidable solution for high-speed serial data transmission, characterized by its robust performance, low power consumption, and versatile configuration options. With these features, it continues to be an essential component in the evolving landscape of electronic communications.