EOS_D_SUM group indicates that at least one of the delta sig- nals below is unmasked and set. NEW_RX_MIN_ERR, NEW_RX_MAX_ERR, NEW_RX_OOS_ERR, NEW_RX_FORM_DEST_ERR, NEW_RX_FIFO_UR_ERR, NEW_RX_FIFO_OF_ERR, NEW_RX_FCS_HEC_ERR, NEW_TX_FIFO_UR_ERR,

OCTETS WITHIN

FRAME ARE

TRANSMITTED FROM

TOP TO BOTTOM

PREAMBLE

START OF FRAME DELIMITER

DESTINATION ADDRESS (DA)

SOURCE ADDRESS (SA)

LENGTH/TYPE

MAC CLIENT DATA

FCS

7OCTETS

1OCTET

6OCTETS

6OCTETS

2OCTETS

46- 1500 OCTETS

4OCTETS

NEW_TX_FIFO_OF_ERR, NEW_TX_ER_ERR, NEW_TX_MII_ALIGN_ERR

MSB

BIT 7

BIT 0

LSB

3.7.4 APS_INTB

Figure 9. An Ethernet MAC frame

RX_APS_INT interrupt message for APS (K1 and K2) indicates that at least one of the RX_K1_D, RX_K2_D, K1_UNSTAB_D is one and the corresponding mask bits and RX_APS_INT_MASK are zero.

3.8 Data Processing

The LAPS and GFP TX Processing refers to the encapsulation of the MAC (Media Access Control) frames coming from the MII (Me- dia Independent Interface, see IEEE 802.3 specification) into the LAPS/GFP frames, which are then sent to the Line Side Interface (SONET/SDH). Figure 9 shows an Ethernet MAC frame, and Figure 10 a LAPS frame with a MAC pay- load.

 

MSB

FLAG (0x7E)

 

MSB

ADDRESS (0x04)

 

MSB

 

 

CONTROL (0x03)

 

MSB

 

 

SAPI MSB (0xFE)

 

 

 

OCTETS WITHIN MSB

SAPI LSB (0x01)

FRAME ARE

 

DESTINATION ADDRESS (DA)

TRANSMITTED FROM

TOP TO BOTTOM

SOURCE ADDRESS (SA)

 

 

 

 

 

 

 

LENGTH/TYPE

 

 

MAC CLIENT DATA

 

 

FCS OF MAC

 

 

FCS OF LAPS

 

 

 

 

 

FLAG (0x7E)

 

 

 

 

MSB

 

MSB

BIT 8

BIT 1

LSB

1 OCTET

LSB

1 OCTET

LSB

1 OCTET

LSB

1 OCTET

LSB

1 OCTET

6OCTETS

6OCTETS

MAC

2 OCTETS FRAME

46 - 1500 OCTETS

4OCTETS

4OCTETS

LSB 1 OCTET

LSB

3.8.1 LAPS Processing

Figure 10. The format of a LAPS frame with a MAC payload

The Transmit LAPS Processor provides the insertion of packet- based information into the STS SPE. It provides packet encapsu- lation, FCS field generation, inter-packet fill and scrambling. The Transmit LAPS Processor performs the following functions:

Encapsulates packets within an LAPS frame. Each packet is encapsulated with a start flag (0x7E), a 32-bit FCS field, Address, Control and SAPI

fields, and an end of field flag (0x7E). All fields except the start flag can be disabled through configuration.

Optional self-synchronous transmit payload scrambler (X43 +1 polynomial).

Transparency processing (octet stuffing for Flags & Control Escape). Byte stuffing occurs between start and end of field flags. Stuffing replaces

each byte within a frame that matches the flag or control code bytes with a two-byte sequence.

Provides the ability to insert FCS errors for testing under SW control.

Provides for selectable treatment of FIFO underflow. A FIFO underflow condition occurs when a TX FIFO empty occurs prior to the end of a

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Agilent Technologies HDMP-3001 manual Apsintb, Laps Processing

HDMP-3001 specifications

Agilent Technologies, a prominent name in electronics and measurement technology, offers a wide range of products that cater to various industries. Among its notable offerings is the HDMP-3001, a high-speed, serial data transceiver designed to facilitate robust communications in electronic systems. The HDMP-3001 stands out with its ability to handle high bandwidths, making it particularly suited for applications requiring rapid data transfer, such as telecommunications, computer networking, and high-performance computing.

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Overall, Agilent Technologies' HDMP-3001 is a formidable solution for high-speed serial data transmission, characterized by its robust performance, low power consumption, and versatile configuration options. With these features, it continues to be an essential component in the evolving landscape of electronic communications.