Agilent Technologies HDMP-3001 manual APS Monitoring, 4.2.10 S1 Monitoring, 4.2.11 M1 Monitoring

3.9.4.2.9 APS Monitoring

If the K1 byte and the four MSBs of the K2 byte, which are used to send APS requests and channel numbers, are received identically for three consecutive frames, their values are written to RX_K1[7:0] and RX_K2[7:4]. Ac- cepted values are compared to the previous contents of these regis- ters, and when a new 12-bit value is stored, the RX_K1_D delta bit is set.

The K1 byte is checked for insta- bility. If, for 12 successive frames, no three consecutive frames are received with identical K1 bytes, the K1_UNSTAB bit is set. It is cleared when three consecutive identical K1 bytes are received. When K1_UNSTAB changes state, the K1_UNSTAB_D delta bit is set. Bits 3 down to 0 of K2 may contain APS mode information. These bits are monitored for

K2_CONSEC[3:0] consecutive identical values. RX_K2[3:0] is written when this occurs, unless the value of bits 2 and 1 of K2 is 11 (indicating Line/MS AIS or RDI). The RX_K2_D delta bit is set when a new value is written to RX_K2[3:0]. The three delta bits associated with APS monitors, RX_K1_D, RX_K2_D and

K1_UNSTAB_D all contribute to an APS interrupt signal, APS_INTB. In addition, these three deltas contribute to the standard summary interrupt sig- nal, INTB.

3.9.4.2.10 S1 Monitoring

The four LSBs of received S1 bytes are monitored for consis- tent values in eight consecutive frames in SONET mode or three consecutive frames in SDH mode. When these bits contain a consis-

tent synchronization status mes- sage, the accepted value is written to RX_S1[3:0].

3.9.4.2.11 M1 Monitoring

The M1 byte indicates the number of B2 errors that were detected by the remote terminal in its received signal. The HDMP-3001 contains a 20-bit M1 error counter that counts every error indicated by M1. The valid values of M1 are 0 to 24; any other value is inter- preted as 0. When the performance monitoring counters are latched, the value of this counter is latched to the

M1_ERRCNT [23:0] register, and the M1 error counter is cleared.

3.9.4.3Transport Overhead Drop

The TOH/SOH drop block outputs the received E1, F1, and E2 bytes and two serial DCC channels.

3.9.4.3.1Orderwire (E1 and E2) and Section User Channel (F1)

The three serial outputs,

RX_E1_DATA, RX_E2_DATA, and RX_F1_DATA, contain the values of the received E1, E2, and F1 bytes. A single 64 kHz clock refer- ence output (RX_E1E2F1_CLK) is provided as well.

3.9.4.3.2Data Communications Channels, DCC, (D1-D12)

There are two DCCs defined in the TOH/SOH. The Section/Regen- erator Section DCC uses the D1, D2, and D3 bytes to create a 192 kb/s channel. The Line/Multiplex Section DCC uses bytes D4 through D12 to create a 576 kb/s channel. The TOH/SOH drop block outputs DCC data on two serial channels, RX_SDCC_DATA and RX_LDCC_DATA. These channels are synchronous to the outputs RX_SDCC_CLK and RX_LDCC_CLK. The DCC data

outputs change on the falling edges of RX_SDCC_CLK and RX_LDCC_CLK.

3.9.4.4Pointer State Determination

Pointer state determination in- volves examining H1-H2 bytes to establish the state of the STS-3c/AU-4 received pointer.

3.9.4.5State Transition Rules

The first pair of H1-H2 bytes con- tain the STS-3c/AU-4 pointer. They are in one of the following three states:

•Normal (NORM = 00)

•Alarm Indication Signal (AIS = 01)

•Loss of Pointer (LOP = 10)

The remaining two pairs of H1-H2 bytes are monitored for correct concatenation indication. They are in one of the following three states:

•Concatenated (CONC = 11)

•Alarm Indication Signal (AISC = 01)

•Loss of Pointer (LOPC = 10)

The individual states are stored in PTR_STATE[1:0], where PTR_STATE[1:0] indicates the state of the H1-H2 bytes. The states of individual pairs of H1-H2 bytes are then combined to deter- mine the state of the STS-3c/AU-4 pointer.

3.9.4.6State of STS-3c/AU-4 Pointer

The HDMP-3001 generates the sta- tus bits RX_PAIS and RX_LOP based on the state of the STS_3c/ AU-4 pointer received.

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