I/O Buffer Types, Tms, Trstb, Tdi | Agilent Technologies HDMP-3001

2.3 I/O Buffer Types

This section lists the types of some particular I/Os used in the HDMP-3001 chip.

Table 8. Buffer types

Buffer Type	I/O Name	Comment

O/D	APS_INTB	Need external P/U
Output

TS	P_RXD_M_TXD[0]	Controlled by the “Isolate MII” register bit
Output	P_RXD_M_TXD[1]
	P_RXD_M_TXD[2]
	P_RXD_M_TXD[3]
	P_RX_DV_M_TX_EN
	P_RX_ER_M_TX_ER

	INT	See INT Pin Configuration Section

	RDYB	Uses a T/S output buffer and logically drives high before output buffer is
		released or tristated

Input	TMS, TRSTB, TDI
w/
Internal P/U

Bidirectional	P_TX_CLK_M_RX_CLK
w/
w/	P_RX_CLK_M_TX_CLK
Internal P/U	P_RX_CLK_M_TX_CLK
for input	SDA	P/U can be disabled if there is an external P/U
mode	SDA	P/U can be disabled if there is an external P/U

	SCL
	SCL

	GPIO [15:0]

Note:

All of the internal P/Us are normally enabled, and they can be disabled through the JTAG port, with the exception of SCL and SDA. The pullups on these two pins can be disabled using controls from register 0x003 bits [5:4].

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Agilent Technologies HDMP-3001 manual I/O Buffer Types, Buffer types Buffer Type Name Comment, Tms, Trstb, Tdi

HDMP-3001 specifications

Agilent Technologies, a prominent name in electronics and measurement technology, offers a wide range of products that cater to various industries. Among its notable offerings is the HDMP-3001, a high-speed, serial data transceiver designed to facilitate robust communications in electronic systems. The HDMP-3001 stands out with its ability to handle high bandwidths, making it particularly suited for applications requiring rapid data transfer, such as telecommunications, computer networking, and high-performance computing.

One of the main features of the HDMP-3001 is its advanced signaling technology. By employing differential signaling, the transceiver minimizes electromagnetic interference and enhances signal integrity. This is crucial in environments with multiple electronic devices operating simultaneously, as it ensures data is transmitted clearly and without degradation.

The HDMP-3001 operates at a maximum data rate of 1 Gbps, allowing for efficient data transfer over short distances. This capability is coupled with a flexible architecture that enables users to configure the transceiver for various applications. The device supports both point-to-point and point-to-multipoint configurations, giving engineers the versatility they need in designing communication links.

Moreover, the HDMP-3001 features on-chip clock recovery functionality, which simplifies system design by reducing the number of external components needed. This built-in feature allows the transceiver to maintain synchronization even as data rates increase, further enhancing performance.

The low power consumption characteristic of the HDMP-3001 is another notable advantage. This makes it an attractive choice for battery-operated devices and systems where power efficiency is critical. The transceiver’s design ensures optimal performance while minimizing heat generation and power draw, enabling longer operational lifetimes.

In terms of physical characteristics, the HDMP-3001 comes in a compact, surface-mount package, allowing for easier integration into various circuit board designs. The small form factor, combined with its innovative technology, makes it a popular choice among engineers seeking to improve data transmission reliability without compromising on space or power constraints.

Overall, Agilent Technologies' HDMP-3001 is a formidable solution for high-speed serial data transmission, characterized by its robust performance, low power consumption, and versatile configuration options. With these features, it continues to be an essential component in the evolving landscape of electronic communications.

Contents

Agilent HDMP-3001 110 116117 118 104 105112 113 STS-3c/STM-1 Configuration for List of Tables See the block diagram HDMP-3001 Features ListInternal Functional Blocks Full Duplex Fast Ethernet Applications BenefitsInterfaces Data Processing Pinout Pin Assignments Receive Loss of Frame Output Receive Line Alarm Indication Signal OutputContinues Loss of Sonettx clock Signal name Pin # TypeI/O Signal descriptionLoss of Sonetrx clock Received E1/E2/F1 Data Reference Clock a Received Line DCC Data Drop output for received Transmit Section DCC Data Input for the Section Transmit Line DCC Data Input for the Line DataTransmit Section DCC Reference Clock BUS Interface Mode Read Enable Active low Write Enable Active low SCL SDAGPIO0 GPIO1 VDD DgndDvdd I/O Buffer Types Buffer types Buffer Type Name CommentPRXDMTXD1 PRXDMTXD2 PRXDMTXD3 Prxdvmtxen Prxermtxer INT TMS, TRSTB, TDI Introduction Interface Descriptions Microprocessor InterfaceMII Management Interface Eeprom Interface Initialization Hardware reset Software ResetSoftware State Machine Reset Bit Order GFP Mode Laps Mode Performance Monitoring Test Loopbacks Loopbacks Jtag pins Signal Name Description Interrupt Driven ModePolled Mode Jtag Apsintb Laps Processing FCS Polynomial for Laps Processing Laps ScramblingGFP Processing FCS Polynomial for GFP Processing GFP Scrambling SONET/SDH Processing Ing Overview 3.1 SPE/VC Structure Signal Label C2 3.2 POHPath Trace J1 Path BIP-8 B3 Prdiauto Prdienh Rxpais Rxuneq Rxplm Rxlop STS-3c/STM-1 TOH/SOH Row Column Pointer Action Byte H3Section Growth/Spare ZO Section Trace Section BIP-8 B1 Line/MS BIP-24 B2 APS Channel and Line/MS AIS/RDI K1 and K2Synchronization Status S1 Line/MS REI M1 4.2.5 B2 Error Counting 4.1 LOCTransport Overhead Monitoring 4.2.1 J0 Monitoring APS Monitoring 4.2.10 S1 Monitoring4.2.11 M1 Monitoring Transport Overhead Drop Current accepted pointer value is incremented by 1 mod Pointer InterpretationPointer Processing Monitor Path Overhead MonitoringSupports two methods Pattern Acceptance and Com Path RDI Monitoring Path REI MonitoringSTS-3C/STM-1 Framer Framer Enabled Details Framer Bypass DetailsIf the framer is bypassed Descrambling 4.14 B1 Monitor Chip setup and configuration Eeprom Detection Configurations PHY and MAC modeSDH and Sonet mode Laps and GFP mode Active value of 0. Refer to Figure HDMP-3001 Pin Name Microprocessor Pin Name BusmodeWRB WE0 RDB Rdyb Intb Cpuclk Clkout Eeprom Interface Configuration COL VSS Register Definitions MII Management Register Map Bit Type Bit Name Default value Description Chip Register Map SONET/SDH Transmit Registers Address Register Name SONET/SDH Transmit Registers SONET/SDH Receive Registers Address Register Name Ethernet Transmit Registers Txsapimsb Ethernet Receive Registers Address Register Name State Global CNT Reset Value After ResetLatch ADDR=0x001 Test Modes Bit DIS SdapuCHIPREV30 PHYADDR40 Rxaps Sumint INT ADDR=0x007 Event Summary Bit TohdsumADDR=0x008 Summary Interrupt Mask Bit Apsintb Mask ADDR=0x009 Mode of Operation Bit Isolate SONET/SDH PHY/MAC GFP/LAPS MIIADDR=0x00A Rx Event Summary Mask Bit Eosd Txuneq Scrinh INHGPIOCTL7 GPIOCTL3 ADDR=0x00E Gpio 70 Data Bit GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0ADDR=0x00F Gpio 158 Data Bit GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 TXB1INV TXB2INV TXB3INV ADDR=0x09D Transmit AIS, RDI, REI Control BitTxlais Lrdiinh Lreiinh TXJ0070 ADDR=0x09F -0x0AE Transmit J0 Bytes 1 BitADDR=0x0B0 Transmit K2 Byte Bit TESTS170 Value After Reset ADDR=0x0B1 Transmit K1 Byte BitADDR=0x0B3 Transmit S1 Byte Bit Preiinh Prdienh Prdiauto Prdi Rxpais Rxuneq Rxplm Auto ENH Rxlop ADDR=0x0F7 POH Error Generation Bit Value 0x18 after ResetTxpais ADDR=0x0F8 Transmit C2 Byte Bit Bit name TXC2 J0OOF Rxlais Rxlrdi RXK1D K1UNSTAB RXK2DW1C Bit J0OOFD J0OOF delta bit Reserved Rxlais RXK1D K1UNSTAB RXK2DDmask Mask Rxoofd Rxlofd Rxlos Rxfram Rxlof Level INH ALG ADDR=0x0FF Receive TOH Monitor Control BitADDR=0x101 Receive Framer Position Control Bit Rxlais Rxlrdi K1UNSTAB S1UNSTAB J0OOF Rxlos ADDR=0x103 Receive SOH Status BitRxoof Rxlof Bits RXK2 70 APS Signaling The received K2 byte Bits 7-0 RXJ0 01570 Section Trace The received 16 J0 bytesADDR=0x114 Receive S1 LSBs Bit ADDR=0x115 Receive K2 Byte Bit Bits B1ERRCNT70 Bits Bits B2ERRCNT70 Bits M1ERRCNT70 ADDR=0x122 Receive Pointer Interpreter Mask Bit Rxlopd Rxpais Mask DmaskADDR=0x126 Receive Pointer Interpreter Delta Bit Rxlopd Rxpais ADDR=0x128 Receive Pointer Status1 Bit PSTATE10Rxlop Rxpais ADDR=0x12A Receive Pointer Status2 Bit ADDR=0x12E Receive J1 Mode Control Bit Content and writes them to RXJ163070 Bit ReservedADDR=0x12D Receive J1 Reading Control Bit J1READ ADDR=0x130 Receive J1 Delta Bit ADDR=0x12F Receive RDI Monitor BitJ1AVLD Reserved Rxuneq Rxplmd J1AVL J1OOFD MaskMask Dmask ADDR=0x133 Receive J1 OOF Bit J1OOFADDR=0x134 -0x173 Receive J1 Bytes Bit RXJ1070 EXPC2 Value After Reset ADDR=0x174 Receive Path Delta BitRXC2D RXG1D Rxuneq Rxplmd ADDR=0x176 Expected C2 Byte Bit ADDR=0x178 Receive Uneq Monitor Bit Reserved RXG120Rxuneq Rxplm Bits 7-0 B3ERRCNT Bits 7-0 G1ERRCNT 70 The lower byte of the G1 error counter Bits 7-0 G1ERRCNT 158 The upper byte of the G1 error counter Value 0x04 After Reset Txscr Txfcs INH CorrAddr = 0x181 Transmit ADR/DPSP Byte Bit TXADRDPSP70 Value 0x03 after Reset Value 0xDD after Reset Value 0x88 after Reset Addr = 0x185 Transmit Fifo Threshold108 MSB BitMSB MSBs of the register above Addr = 0x186 Transmit Laps mode Bit Txadr Txcnt Txsapi Txabort Txra INHBits Reserved Txcore Txext Txtype Hdinh HEC Hdrinh Corr Value 0xFE after Reset Value 0x01 after ResetAddr = 0x189 Transmit Sapi MSB Bit Bit name TXSAPIH70 Txmiiframesrecok AddrTxmiialignerr Addr = 0x194-0x197 Txer Error Counter Addr = 0x198-0x19B TX Fifo Overflow Error0x19A Fixed 0x19B Value After Reset Bit Bit name 0x198 Newtx Fifour Fifoof Ererr Miialign ERR Newtx Fifour Fifoof Ermask Miialign Mask Addr = 0x1A1 Ethernet Transmit Interrupt Mask BitInterrupt event bit Value 0xA4 after Reset Ethernet Receive Registers Addr = 0x1C0 GFP/LAPS Mode BitRxdes Rxfcs INH Reminh RXFIFOTHRESHOLD108 Addr = 0x1C3 RX Fifo Transmit Threshold108 BitHIIFGWATERMARK70 HIIFGWATERMARK108 Addr = 0x1C5 High Inter-Frame-Gap Water Mark BitLOIFGWATERMARK70 Addr = 0x1C7 Low Inter-Frame-Gap Water Mark Bit LOIFGWATERMARK108Addr = 0x1C8 Normal Inter-Frame-Gap Bit NORMALIFG40 Reserved LOWIFG40 Value 0x0A After Reset Addr = 0x1C9 Low Inter-Frame-Gap BitBits 7-5 Reserved Addr = 0x1CA Receive ADR/TYPEL Bit Bit name Rxadrtypel Addr = 0x1CB Receive Control/TYPEH Bit Bit name Rxcnttypeh Addr = 0x1CD Laps Mode Bit Rxadr Rxcnt Rxsapi Reminh Check INH Value 0x00 after Reset Addr = 0x1CE GFP Mode BitRxext Addr = 0x1D0 Receive Pre-Sync States Bit RXPRESYNC30Addr = 0x1D1 Receive Sapi LSB Bit Bit name RXSAPIL70 Addr = 0x1D2 Receive Sapi MSB Bit Bit name RXSAPIH70 Rxmiiframesxmitok RX Formdesterr Rxsyncerr Addr = 0x1E4-E7 Receive Fifo Overflow Error 0x1E6 Fixed 0x1E7 Value After ResetAddr = 0x1E8-EB Receive Fifo Underrun Error 0x1EA Fixed 0x1EB Value After Reset ERR W1C Addr = 0x1EC Ethernet Receive Interrupt Event BitCounter Addr = 0x1ED Ethernet Receive Interrupt Mask Bit Newrx Newrx MIN MAX OOS Form Fifour Fifoof Rxmin RXMINSIZE60 Enforce Rxmax Addr = 0x1F4-7 Receive Minimum Frame Size Violations Addr = 0x1F8-B Receive Maximum Frame Size Violations HDMP-3001 LLLLLLLLL-NNN Yyww R.R Ccccc Lllllllll Wafer LOT Number Bottom View of Package Package Dimensions Symbol Min Nom Max Comment Symbol Parameter Units Typ Max TechnologyMicron CMOS, 1.8V core and 3.3V I/Os ESD DC Characteristics AC Electrical CharacteristicsPower Dissipation IL/IIH Ptxdmrxd Ptxdvmrxen Ptxermrxer ↑ Ptxclkmrxclk Prxdmtxd Prxdvmtxen Prxermtxer ↑ PrxclkmtxclkPtxdmrxd Ptxdvmrxen Ptxermtxer ↑ Ptxclkmrxclk Timing Diagrams Microprocessor Bus Timing Write Cycle Microprocessor Bus Timing Read Cycle Microprocessor Read Cycle Timing Line Interface Receive and Transmit Timing Parameter Description Min ns Max nsLabel Parameter Min Max Units TOH Interface E1/E2/F1 Transmit Timing Label Parameter Min Typ Max Units TOH Interface E1/E2/F1 Receive Timing DCC Interface Transmit Timing DCC Interface Receive Timing Jtag Interface Timing Reset specification MII Timing MII signal clocking Mode Direction Pin name In/Out Mdio Port Timing MIN MAX Units Eeprom Port Timing Eeprom Interface Timing ParametersFrame Declaration 119 120 121 122 Receive Data Link Clock and Data Alignment Applicable Documents

2.3 I/O Buffer Types

Table 8. Buffer types

Buffer Type

I/O Name

Comment

P_RXD_M_TXD[1]

P_RXD_M_TXD[2]

P_RXD_M_TXD[3]

P_RX_DV_M_TX_EN

P_RX_ER_M_TX_ER

INT

RDYB

TMS, TRSTB, TDI

P_TX_CLK_M_RX_CLK

P_RX_CLK_M_TX_CLK

SDA

SCL

GPIO [15:0]

HDMP-3001 specifications