ADDR=0x007: Event Summary

 

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit name

TOH_D_SUM

Reserved

PTR_D_SUM

POH_D_SUM

Reserved

EOS_D_SUM

Reserved

Reserved

 

 

 

 

 

 

 

 

 

R/W

R

R

R

R

R

 

 

 

 

 

 

 

 

 

Value

0

0

0

0

0

0

0

0

after

 

 

 

 

 

 

 

 

reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit 7: TOH_D_SUM is set to indicate at least one of the TOH/SOH delta bits (RX_LOS_D, RX_OOF_D, RX_LOF_D, RX_LAIS_D, RX_LRDI_D, J0_OOF_D) is set and its corresponding mask bit is cleared.

Bit 6: Reserved

Bit 5: PTR_D_SUM is set to indicate at least one of the Pointer Interpreter delta bits (RX_PAIS_D, RX_LOP_D) is set and its corresponding mask bit is cleared.

Bit 4: POH_D_SUM RX_UNEQ_D, cleared.

is set to indicate at least one of the Path Monitoring delta bits (RX_PLM_D, RX_G1_D, J1_OOF_D, J1_AVL, RX_C2_D) is set and its corresponding mask is

Bit 3: Reserved

Bit 2: EOS_D_SUM is set to indicate at least one of the delta signals (NEW_RX_OOS_ERR, NEW_RX_FORM_DEST_ERR, NEW_RX_FIFO_UR_ERR, NEW_RX_FIFO_OF_ERR, NEW_RX_FCS_HEC_ERR, NEW_TX_FIFO_UR_ERR, NEW_TX_FIFO_OF_ERR, NEW_TX_ER_ERR, NEW_TX_MII_ALIGN_ERR) is set and enabled.

Bits 1-0: Reserved

ADDR=0x008: Summary Interrupt Mask

 

 

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

 

Bit name

Reserved

Reserved

Reserved

Reserved

Reserved GROUP_

RX_APS_INT_

SUM_INT_

 

 

 

 

 

 

 

APS_INTB

MASK

MASK

 

R/W

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

Value

0

0

0

0

0

1

1

1

 

after

 

 

 

 

 

 

 

 

 

reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits 7-3:

Reserved

 

 

 

 

 

 

 

Bit 2:

GROUP_APS_INTB: If 1, it sets all unmasked RX_APS_INT alarms, SUM_INT bit and APS_INT

 

 

pin. This mode is useful in configuration where only one interrupt line on the CPU is used and is

 

 

connected to the INTB pin. If 0, it inhibits the RX_APS_INT alarms from affecting the SUM_INT bit.

 

 

This mode is useful in configuration where APS_INT and INTB are connected to separate interrupt

 

 

lines.

 

 

 

 

 

 

 

Bit 1:

RX_APS_INT_MASK is set to enable the HDMP-3001 interrupt output pin APS_INTB.

Bit 0:

SUM_INT_MASK is set to enable the HDMP-3001 interrupt output pin INTB.

 

52

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Image 52
Agilent Technologies HDMP-3001 ADDR=0x007 Event Summary Bit, Tohdsum, ADDR=0x008 Summary Interrupt Mask Bit, Apsintb Mask

HDMP-3001 specifications

Agilent Technologies, a prominent name in electronics and measurement technology, offers a wide range of products that cater to various industries. Among its notable offerings is the HDMP-3001, a high-speed, serial data transceiver designed to facilitate robust communications in electronic systems. The HDMP-3001 stands out with its ability to handle high bandwidths, making it particularly suited for applications requiring rapid data transfer, such as telecommunications, computer networking, and high-performance computing.

One of the main features of the HDMP-3001 is its advanced signaling technology. By employing differential signaling, the transceiver minimizes electromagnetic interference and enhances signal integrity. This is crucial in environments with multiple electronic devices operating simultaneously, as it ensures data is transmitted clearly and without degradation.

The HDMP-3001 operates at a maximum data rate of 1 Gbps, allowing for efficient data transfer over short distances. This capability is coupled with a flexible architecture that enables users to configure the transceiver for various applications. The device supports both point-to-point and point-to-multipoint configurations, giving engineers the versatility they need in designing communication links.

Moreover, the HDMP-3001 features on-chip clock recovery functionality, which simplifies system design by reducing the number of external components needed. This built-in feature allows the transceiver to maintain synchronization even as data rates increase, further enhancing performance.

The low power consumption characteristic of the HDMP-3001 is another notable advantage. This makes it an attractive choice for battery-operated devices and systems where power efficiency is critical. The transceiver’s design ensures optimal performance while minimizing heat generation and power draw, enabling longer operational lifetimes.

In terms of physical characteristics, the HDMP-3001 comes in a compact, surface-mount package, allowing for easier integration into various circuit board designs. The small form factor, combined with its innovative technology, makes it a popular choice among engineers seeking to improve data transmission reliability without compromising on space or power constraints.

Overall, Agilent Technologies' HDMP-3001 is a formidable solution for high-speed serial data transmission, characterized by its robust performance, low power consumption, and versatile configuration options. With these features, it continues to be an essential component in the evolving landscape of electronic communications.