Ampro Corporation 486E manual Pin Signal Description Name, Flm

Little Board™/486e Technical Manual

Table 2–30. Flat Panel Video Connector (J3)

Pin	Signal	Description
	Name
2, 34, 37	+5V	+5 Volt supply from the Little Board/486e CPU
3	+12V	+12 Volt supply from J10
5	ShfClk	Shift Clock. Pixel clock for flat panel data. Sometimes called
		Video Clock.
7	M	M signal for panel AC drive control. Sometimes called ACDCLK
		or AC Drive. May also be configured to be -BLANK or as Display
		Enable (DE) for TFT panels.
9	LP	Latch Pulse. Sometimes called Load Clock, Line Load, or Input
		Data Latch, the flat panel equivalent of HSYNC.
10	FLM	First Line Marker. Also called Frame Sync or Scan Start-up. Flat
		panel equivalent to VSYNC.
12 – 31	VD0 – VD19	Panel video data 0 through 19 (in order). For 8-, 9-, 12-, or 16-bit
		flat panels.
36	ENABKL	Enable backlight. Power control for panel backlight. Active High,
		same as ENAVEE.
38	ENAVEE	Enable Vee. Power sequencing control for panel bias voltage.
		Active high.
39	ENAVDD	Enable Vdd. Power sequencing control for panel driver
		electronics Vdd. Active high.
41	VD20	Video data 20
42	VD21	Video data 21
43	VD22	Video data 22
44	VDDSAFE	Swiched power supply to panel
45	VD23	Video data 23
46	VEE	Switched Vee supply to panel from LCD Bias Supply
47	EXTCONT	External contrast adjustment to LCD Bias Supply
50	+12VSAVE	Switched +12V supply to panel
1, 4, 6, 8,	Ground	Ground
40, 48, 49
11, 32, 33,	N/C	No connection
35

2–36