Little Board™/486e Technical Manual
2–36
Table 2–30. Flat Panel Video Connector (J3)
Pin Signal
Name Description2, 34, 37 +5V +5 Volt supply from the L ittle Boar d/48 6e CPU
3 +12V +12 Volt supply from J10
5 ShfClk Shift Clock. Pixel cl ock f or flat pan el da ta. S om etim es c alled
Video Clock.
7 M M signal for panel AC dr ive c ontr ol. Som etim es c alled ACDCL K
or AC Drive. May also be configured to be -BLANK or as Dis pla y
Enable (DE) for TFT panels.
9 LP Latch Pulse. Sometimes called Load Clock, Line Load, or Inp ut
Data Latch, the flat panel equivalent of HSYNC.
10 FLM First Line Marker. Also called Fram e Sync or Sc an St art-up . Flat
panel equivalent to VSYNC.
12 – 31 VD0 – VD19 Panel video data 0 through 19 (in order). For 8-, 9-, 12-, or 16-bit
flat panels.
36 ENABKL Enable backlight. Power control for panel backlight. Act ive High,
same as ENAVEE.
38 ENAVEE Enable Vee. Power sequ enci ng c ontr ol for pa nel b ias volt age.
Active high.
39 ENAVDD Enable Vdd. Power sequencing c ontr ol for pa nel dr ive r
electronics Vdd. Active high.
41 VD20 Video data 20
42 VD21 Video data 21
43 VD22 Video data 22
44 VDDSAFE Swiched power supply to panel
45 VD23 Video data 23
46 VEE Switched Vee supply to panel from LCD Bi as Su ppl y
47 EXTC ONT External contrast adjustment to LCD Bias S uppl y
50 +12VSAVE Switched +12V supply to panel
1, 4, 6, 8,
40, 48, 49 Ground Ground
11, 32, 33,
35 N/C No connec tio n