A15 | Analog Devices ADSP-2192 manual

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For current information contact Analog Devices at (781) 461-3881

ADSP-2192

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October 2000

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Table 8. 24I-bit PCI DSP Memory Map (BAR 2 Mode) (Continued)

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Byte3

Byte2

Byte1

Byte0

Offset

Block

T

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D

UNUSED

D[15:8]

D[7:0]

UNUSED

0x0009 0000

DSP P1 Data RAM Block 1

UNUSED

D[15:8]

D[7:0]

UNUSED

0x0009 0004

:

UNUSED

D[15:8]

D[7:0]

UNUSED

0x0009 FFFC

Reserved Space.

UNUSED

D[15:8]

D[7:0]

UNUSED

0x000A 0000

UNUSED

D[15:8]

D[7:0]

UNUSED

0x000A 0004

:

UNUSED

D[15:8]

D[7:0]

UNUSED

0x000B FFFC

DSP P1 Program RAM Block

UNUSED

D[23:16]

D[15:8]

D[7:0]

0x000C 0000

UNUSED

D[23:16]

D[15:8]

D[7:0]

0x000C 0004

:

UNUSED

D[23:16]

D[15:8]

D[7:0]

0x000C FFFC

DSP P1 Program ROM Block

UNUSED

D[23:16]

D[15:8]

D[7:0]

0x000D 0000

UNUSED

D[23:16]

D[15:8]

D[7:0]

0x000D 0004

:

UNUSED

D[23:16]

D[15:8]

D[7:0]

0x000D 3FFC

Reserved Space

RESERVED

RESERVED

RESERVED

RESERVED

0x000D 4000

:

RESERVED

RESERVED

RESERVED

RESERVED

0x000F FFFC

16-bit PCI DSP Memory Map (BAR3)

The Complete PCI Address Footprint for the ADSP-2192

DSP Memory Spaces in 16-bit (BAR 3) Mode is as follows:

Table 9. 16-bit PCI DSP Memory Map (BAR 3 Mode)

Block

Byte3

Byte2

Byte1

Byte0

Offset

DSP P0 Data RAM Block 0

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D[7:0]

D[15:8]

D[7:0]

0x0000 0000

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0000 0004

:

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0000 7FFC

DSP P0 Data RAM Block 1

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0000 8000

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0000 8004

:

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0000 FFFC

DSP P0 Data RAM Block 2

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0001 0000

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0001 0004

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D[15:8]

D[7:0]

D[15:8]

D[7:0]

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0x0001M7FFC A

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REV. PrA

This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

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Image 15

Analog Devices ADSP-2192 specifications A15

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.

Contents

Preliminary Technical Data Words on-chip 16-bit RAM for Data Memory and 16K 48K words of on-chip RAM on P1, configured as 32K REV. PrA Rupts. a 16-bit count register Tcount is decremented Programmable interval timer generates periodic inter Output DSP-DSP Semaphore DSP-DSP Interrupt DSP-DSP ADSP-2192 Loop stack interrupt enable Ification. This interface supports the high data rates Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Pliant codecs to the ADSP-2192. The ACLink implements BAR3 registers appear in on page 14 and Table DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 DSP, using the REG instruction Mode the functions of the registers are mapped as follows Rpci Dmah controller can be programmed to perform scatADSP-2192 without processor intervention. In scat Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master Transactions Bist Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access Register or memory location within the ADSP-2192. Simi Inta Data Word. BAR3 Mode is typically used for Data Memory PCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Reserved Unused A15 9FFC 7FFC 0x8-0x9 DSP Memory Buffer WR Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x6-0x7 DSP Memory Buffer RD Offset EP8 EP5EP6 EP7 Device-specific attributes returned in the GET Descriptor command is contained in this register.Release Number returned in the GET Device Release Number is 0x0100, which corresponds to USB EP7 NAK USB EP4 NAKUSB EP5 NAK USB EP6 NAK A21 Fixed Endpoints Control Endpoint ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU ThisR registerHprovides information as the total size 0x01 0x02 0x00 ADIREV. PrA A23 XXX USB Mcucode Address USB RegioBRequest 0xA0 WValue L WValue H A27 If for some reason the host sends more data than the max Packetsize, theNUSB core accepts it, as long as there isSufficientCroom in theAFIFO Pmeen output from the Combo Master should Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP An active lowIRST input to be derived from PCI RST Fifo Is shown as a no connect in on page 33 these SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only ADSP-2192 can be clocked by a crystal oscillator. If a ADSP-2192 Boot Process Flow ForEthis configuration.T Manufacturer.I a parallel-resonant, fundamental frequencyRmicroprocessorH -grade 24.576 MHz crystal should be used Run-time library that includes DSP and mathematical func Tion-level simulator a C/C++ compiler and a C/C++ A35 AD3 AD0AD1 AD2 131 128 PCI / ISA Interrupt CBE0 CBE1 CBE2 CBE3 CLK130 Clkrun Devsel Frame GNT Idsel Intab Pcivdd IrdyPAR Pcignd Emulator Event Pin Emulator Clock Input Emulator Data Input Emulator Mode Select Emulator Logic ResetEmulator Data Output Acvaux Aiognd Avdd Ctrlaux Ctrlvdd IgndIvdd Rvaux Rvdd TBD Specifications are subject to change VIN=2.5V Supply Current Dynamic @ 160 Mips InternalSupply Current Idle Input Capacitance6 FIN=1 MHz IOR / IOW Strobe Width 100 AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling Write Data Setup to IOW Rising Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide