Analog Devices ADSP-2192 specifications Dsp-Dsp, Output DSP-DSP Semaphore DSP-DSP Interrupt

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R

For current information contact Analog Devices at (781) 461-3881

ADSP-2192

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October 2000

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M

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Table 2 on page 5 shows the interrupt vector and

mechanismsIto generate a 24-bit address for each bus. The

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DSP-to-DSP semaphores at reset of each of the peripheral

RDSP hasHthree functions that support access to the full

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C

A

interrupts. The peripheral interrupt’s position in the

memoryE

map.T

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A

IMASK and IRPTL register and its vector address depend

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• The DAGs generate 24-bit addresses for data fetches

on its priority level, as shown in Table 1 on page 5.

from the entire DSP memory address range. Because

DAG index (address) registers are 16 bits wide and

Table 1. Interrupt Vector Table

hold the lower 16-bits of the address, each of the DAGs

has its own 8-bit page register (DMPGx) to hold the

Vector

most significant eight address bits. Before a DAG gen-

Priorit

Bit

Interrupt

Address

erates an address, the program must set the DAG’s

y

Offset1

DMPGx register to the appropriate memory page.

• The Program Sequencer generates the addresses for

0

1

Reset (non-maskable)

0x00

instruction fetches. For relative addressing instruc-

1

2

Powerdown

0x04

tions, the program sequencer bases addresses for

(non-maskable)

relative jumps, calls, and loops on the 24-bit Program

Counter (PC). In direct addressing instructions

2

3

Kernel interrupt (single

0x08

(two-word instructions), the instruction provides an

step)

immediate 24-bit address value. The PC allows linear

addressing of the full 24 bit address range.

3

4

Stack Status

0x0C

• For indirect jumps and calls that use a 16-bit DAG

4

5

Mailbox

0x10

address register for part of the branch address, the Pro-

gram Sequencer relies on an 8-bit Indirect Jump page

5

6

Timer

0x14

(IJPG) register to supply the most significant eight

6

7

Reserved

0x18

address bits. Before a cross page jump or call, the pro-

gram must set the program sequencer’s IJPG register to

7

8

PCI Bus Master

0x1C

the appropriate memory page.

Each ADSP-219x DSP core has an on-chip ROM that

8

9

DSP-DSP

0x20

holds boot routines. For more information, see “Booting

9

10

FIFO0 Transmit

0x24

Modes” on page 31.

Interrupts

10

11

FIFO0 Receive

0x28

The interrupt controller lets the DSP respond to thirteen

11

12

FIFO1 Transmit

0x2C

interrupts with minimum overhead. The controller imple-

12

13

FIFO1 Receive

0x30

ments an interrupt priority scheme as shown in Table 1 on

page 5. Applications can use the unassigned slots for soft-

13

14

Reserved

0x34

ware and peripheral interrupts. The DSP’s Interrupt

Control (ICNTL) register (shown in Table 3 on page 6)

14

15

Reserved

0x38

provides controls for global interrupt enable, stack interrupt

15

16

AC’97 Frame

0x3C

configuration, and interrupt nesting.

1 The interrupt vector address values are represented as offsets from address 0x01 0000. This address corresponds to the start of Program Memory in DSP P0 and P1.

Table 2. DSP-to-DSP Semaphores Register Table

REV. PrA

								DSP
	Flag	Direct-	Function					Core
	Bit	ion						Flag
								In
	0	Output	DSP-DSP Semaphore 0							Y
	1	Output	DSP-DSP Semaphore 1						R
								A
							N			L
	2	Output	DSP-DSP Interrupt			I
				M					A
				I				C
			L
			E					I
						N
			R		H
This information applies to a product under development. Its characteristics and specifications are subjectPto change with-									A5
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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.								T
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