PRELIMINARY
TECHNICAL
DATA
PRELIMINARY
TECHNICAL
DATA
For current information contact Analog Devices at (781) 461-3881
ADSP-2192 October 2000
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
30 REV. PrA
When communicating with the AC'97 interface, the Con-
nection Enable bits in the control register are set to '10'.
Bit 3 selects stereo or mono transfers to and from the AC'97
interface. Bits 7-4 select the AC'97 slot associated with this
FIFO.
When stereo is selected, the slot identified and the next slot
are both associated with the FIFO. Typically, stereo is
selected for left and right data, and both left and right must
be associated with the same external AC'97 codec and have
their sample rates locked together. In this case, left and right
data will alternate in the FIFO with the left data coming
first.
If the FIFO is enabled for the AC'97 interface, and a valid
request for data comes along that the FIFO cannot fulfill,
the transmitter underflow bit is set, indicating that an
invalid value was sent over the selected slot. Similarly, on
the receive side, if the FIFO is full and another valid word
is received, the Overflow bit is sent to indicate the loss of
data.
FIFO Control Registers
The Transmit FIFO Control Register has the following bit
field definitions:
•CE (Bits 1–0): Connection Enable (00 = Disable,
01 =Reser ved, 10 = Connect to AC’97, and 11 =
Reserved)
•DPSel (Bit 2): Reserved (0 )
•SMSel (Bit 3): Stereo / Mono Select - AC’97 Mode
Only (0 = Mono Stream or 1 = Stereo Stream)
•SLOT (Bits 7–4): AC’97 Slot Select - AC’97 Mode
Only
•FIP (Bits 10–8): FIFO interrupt position. An interrupt
is generated when FIP[2:0] Words remain in the FIFO.
The interrupt is level-sensitive.
•DME (Bit 11): DMA Enable. (0 = DMA Disabled or
1 = DMA Enabled)
•TFF (Bit 13): Transmit FIFO Full - Read Only.
(0 = FIFO Not Full or 1 = FIFO Full)
•TFE (Bit 14): Transmit FIFO Empty - Read Only. (0 =
FIFO Not Empty or 1 = FIFO Empty)
•TU (Bit 15): Transmit Underflow - Sticky, Write “1”
Clear. (0 = FIFO Underflow has not occurred or
1 = FIFO Underflow has occurred)
The Receive FIFO Control Register has the following bit
field definitions:
•CE (Bits 1–0): Connection Enable. (00 = Disable,
01 =Reser ved, 10 = Connect to AC’97, 11 =
Reserved)
•DPSel (Bit 2): Reserved (0)
Table 25. AC’97 Slot Select Values
Slot Mono Stereo
0000–0010 Reserved
0011 Slot 3 Slots 3/4
0100 Slot 4 Slots 4/5
0101 Slot 5 Slots 5/6
0110 Slot 6 Slots 6/7
0111 Slot 7 Slots 7/8
1000 Slot 8 Slots 8/9
1001 Slot 9 Slots 9/10
1010 Slot 10 Slots 10/11
1011 Slot 11 Slots 11/12
1100 Slot 12 Not Allowed
1101–1111 Reserved