REV. PrA
This register contains an 18 bit address which corresponds to the starting location for DSP code download on endpoint 2. This register is read/write by the MCU only.
USB Endpoint 1 Code Download Base Address Register
This register contains an 18 bit address which corresponds to the starting location for DSP code download on endpoint 1. This register is read/write by the MCU only.
USB Endpoint 2 Code Download Base Address Register

 

 

 

 

 

 

 

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A

 

For current information contact Analog Devices at (781) 461-3881

 

 

 

 

October 2000

ADSP-2192

 

 

 

 

 

 

 

 

 

 

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USB Endpoint 3 Code Download Base Address

 

 

USB EndpointI

Description Register

 

E

 

N

 

 

Register

 

R

 

H

A

 

 

P

 

 

 

 

 

 

 

 

 

The endpoint description register provides the USB core

 

 

 

 

 

 

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T

 

 

This register contains an 18 bit address which corresponds

 

 

withE information about the endpoint type, direction, and

 

T

 

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D

 

 

 

to the starting location for DSP code download on

 

 

max packet size. This register is read/write by the MCU

 

 

only. This register is defined for endpoints 4-11.

endpoint 3. This register is read/write by the MCU only.

•PS[9:0] MAX Packet Size for endpoint

•LT[1:0] Last transaction indicator bits: 00 = Clear, 01 = ACK, 10 = NAK, or 11 = ERR

•TY[1:0] Endpoint type bits: 00 = DISABLED, 01 = ISO, 10 = Bulk, or 11 = Interrupt

•DR Endpoint direction bit: 1 = IN or 0 = OUT

•TB Toggle bit for endpoint. Reflects the current state of the DATA toggle bit.

USB Endpoint NAK Counter Register

This register records the number of sequential NAKs that have occurred on a given endpoint. This register is defined for endpoints 4-11. This register is read/write by the MCU only.

•N[3:0] NAK counter. Number of sequential NAKs that have occurred on a given endpoint. When N[3:0] is equal to the base NAK counter NK[3:0], a zero-length packet or packet less that maxpacketsize will be issued.

•ST 1 = Endpoint is stalled

USB Endpoint 1 Code Current Write Pointer Offset Register

This register contains an 18 bit address which corresponds to the current write pointer offset from the base address reg- ister for DSP code download on endpoint 1. The sum of this register and the EP1 Code Download Base Address Register represents the last DSP PM location written.

This register is read by the MCU only and is cleared to 3FFFF (-1) when the Endpoint 1 Code Download Base Address Register is updated.

USB Endpoint 2 Code Current Write Pointer Offset Register

This register contains an 18 bit address which corresponds to the current write pointer offset from the base address reg- ister for DSP code download on endpoint 2. The sum of this register and the EP2 Code Download Base Address Register represents the last DSP PM location written.

This register is read by the MCU only and is cleared to 3FFFF (-1) when the Endpoint 2Code Download Base Address Register is updated.

USB Endpoint Stall Policy Register

This register contains NAK count and endpoint FIFO error policy bit. The STALL status bits for endpoints 1-3 are included as well. This register is read/write by the MCU only.

•ST[3:1] 1 = Endpoint is stalled. ST[1] maps to end- point 1, ST[2] maps to endpoint 2, etc.

•NK[3:0] Base NAK counter. Determines how many sequential NAKs are issued before sending zero length packet on any given endpoint.

•FE FIFO error policy. 1 = When endpoint FIFO is overrun/underrun, STALL endpoint

USB Endpoint 3 Code Current Write Pointer Offset Register

This register contains an 18 bit address which corresponds to the current write pointer offset from the base address reg- ister for DSP code download on endpoint 3. The sum of this register and the EP3 Code Download Base Address Register represents the last DSP PM location written.

This register is read by the MCU only and is cleared to 3FFFF (-1) when the Endpoint 3Code Download Base Address Register is updated.

USB SETUP Token Command Register

This register is defined as 8 bytes long and contains the data sent on the USB from the most recent SETUP transaction. This register is read by the MCU only.

USB SETUP Token Data Register

If the most recent SETUP transaction involves a data OUT stage, this register is defined as 8 bytes long and contains the data sent on the USB during the data stage. This is also where the MCU will write data to be sent in response to a SETUP transaction involving a data IN stage. This register is read/write by the MCU only.

 

 

 

 

 

 

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A21

 

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This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

 

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Analog Devices ADSP-2192 specifications A21
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ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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