Figure 1 on page 1 shows the architecture of the ADSP-219xdual-core DSP. Each core contains three inde- pendent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The compu- tational units process 16-bit data from the register file and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations. The MAC has two 40-bit
DSP Core Architecture
The ADSP-2192 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single-word instruction can be executed in a single processor cycle. The ADSP-2192 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.

 

 

 

 

 

 

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For current information contact Analog Devices at (781) 461-3881

ADSP-2192

 

 

 

 

 

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sequencer make the ADSP-2192 more

accumulators, which help with overflow. The shifter per-

 

 

tors, and programI

 

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forms logical and arithmetic shifts, normalization,

RflexibleHand even easier to program than the

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denormalization, and derive exponent operations. The

 

 

ADSPE -218xTDSPs.

 

 

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shifter can be used to efficiently implement numeric format

 

 

 

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Indirect addressing options provide addressing flexibility—

control, including multiword and block floating-point

 

 

premodify with no update, post-modify with update, pre-

 

 

representations.

 

 

 

and post-modify by an immediate 8-bit, two’s-complement

 

 

 

 

 

 

 

value and base address registers for easier implementation

Register-usage rules influence placement of input and

 

 

of circular buffering.

 

results within the computational units. For most operations,

 

 

The ADSP-2192 integrates 64K words of on-chip memory

the computational units’ data registers act as a data register

 

 

file, permitting any input or result register to provide input

 

 

configured as 32K words (24-bit) of program RAM, and

 

 

to any unit for a computation. For feedback operations, the

 

 

96K words (16-bit) of data RAM. Power-down circuitry is

 

 

computational units let the output (result) of any unit be

 

 

also provided to meet the low power needs of battery oper-

 

 

input to any unit on the next cycle. For conditional or mul-

 

 

ated portable equipment. The ADSP-2192 is available in a

 

 

tifunction instructions, there are restrictions on which data

 

 

144-lead LQFP package.

 

 

 

 

registers may provide inputs or receive results from each

 

 

Fabricated in a high speed, low power, CMOS process, the

 

 

computational unit. For more information, see the

 

 

ADSP-2192 operates with a 6.25-ns instruction cycle time

 

 

ADSP-219x DSP Instruction Set Reference.

 

 

(160 MIPS). All instructions, except two multiword

 

 

A powerful program sequencer controls the flow of instruc-

 

 

instructions, can execute in a single DSP cycle.

 

 

tion execution. The sequencer supports conditional jumps,

 

 

The ADSP-2192’s flexible architecture and comprehensive

 

 

subroutine calls, and low interrupt overhead. With internal

 

 

instruction set support multiple operations in parallel. For

 

 

loop counters and loop stacks, the ADSP-2192 executes

 

 

example, in one processor cycle, each DSP core within the

 

 

looped code with zero overhead; no explicit jump instruc-

 

 

ADSP-2192 can:

 

 

 

 

 

 

tions are required to maintain loops.

 

 

 

 

 

 

 

 

 

 

 

 

 

• Generate an address for the next instruction fetch

Two data address generators (DAGs) provide addresses for

 

 

• Fetch the next instruction

 

 

 

 

simultaneous dual operand fetches. Each DAG maintains

 

 

• Perform one or two data moves

and updates four 16-bit address pointers. Whenever the

 

 

• Update one or two data address pointers

pointer is used to access data (indirect addressing), it is pre-

 

 

or post-modified by the value of one of four possible modify

 

 

• Perform a computational operation

 

 

registers. A length value and base address may be associated

 

 

 

 

 

 

 

 

 

 

 

These operations take place while the processor

with each pointer to implement automatic modulo address-

 

 

continues to:

 

 

 

ing for circular buffers. Page registers in the DAGs allow

 

 

• Receive and/or transmit data through the Host port

linear or circular addressing within 64 Kword boundaries of

 

 

each of the memory pages, but these buffers may not cross

 

 

 

(PCI or USB interfaces)

 

 

 

 

 

page boundaries. Secondary registers duplicate all the pri-

 

 

• Receive or transmit data through the AC’97

 

 

mary registers in the DAGs; switching between primary and

 

 

• Decrement the two timers

 

 

 

 

secondary registers provides a fast context switch.

Efficient data transfer in the core is achieved with the use of internal buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

REV. PrA

Program memory can store both instructions and data, per- mitting the ADSP-2192 to fetch two operands in a single cycle, one from program memory and one from data mem- ory. The DSP’s dual memory buses also let the ADSP-2192 core fetch an operand from data memory and the next instruction from program memory in a single cycle.

 

 

 

 

 

 

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This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

 

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Page 3
Image 3
Analog Devices ADSP-2192 specifications REV. PrA

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.