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| For current information contact Analog Devices at (781) |
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| October 2000 |
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| PCI Base Address Register (BAR 4) allows indirect access |
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| to the |
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| The DSP Memory Indirect Access Registers accessible |
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| from BAR4 are as follows: |
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| Table 10. |
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| Offset |
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| Name |
| Reset | Comments |
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| Control Register Address | 0x0000 | Address and direction control for registers accesses | |||||
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| Control Register Data | 0x0000 | Data for register accesses |
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| DSP Memory Address | 0x000000 | Address and Direction control for Indirect DSP | |||||
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| memory accesses |
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| DSP Memory Data | 0x000000 | Data for DSP memory accesses |
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DSP P0 Memory Indirect Address Space occupies PCI BAR4 Space 0x000000
DSP P1 Memory Indirect Address Space occupies PCI BAR4 Space 0x020000
All Indirect DSP Memory Accesses are
Using the USB Interface
The
1.Programmable descriptors and a
2.A total of 8
USB DSP Register Definitions
For each endpoint, four registers are defined to provide a memory buffer in the DSP. These registers are defined for each endpoint shared by all defined interfaces, for a total of 4x8 = 32 registers. These registers are read/write by the DSP only.
Table 11. USB DSP Register Definitions
Page
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
REV. PrA
Address | Name |
| Comment |
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| DSP Memory Buffer Base Addr |
| EP4 |
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| DSP Memory Buffer Size |
| EP4 |
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| DSP Memory Buffer RD Offset |
| EP4 |
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| DSP Memory Buffer WR Offset |
| EP4 |
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| DSP Memory Buffer Base Addr |
| EP5 |
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| DSP Memory Buffer Size |
| EP5 |
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| DSP Memory Buffer RD Offset |
| EP5 |
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This information applies to a product under development. Its characteristics and specifications are subjectPto change with- |
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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing. |
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