Analog Devices ADSP-2192 specifications SMSelIBit 3 Stereo / Mono Select AC’97 Mode

REV. PrA

Power On Reset

USB Reset

PCI Reset

Power On Reset

System Reset Description

There are several sources of reset to the ADSP-2192.

RO (Bit 15): Receive Overflow - Sticky, Write-One-Clear. (0 = FIFO Overflow has not occurred or 1 = FIFO Overflow has occurred)

RFE (Bit 14): Receive FIFO Empty - Read Only. (0 = FIFO Not Empty or 1 = FIFO Empty)

RFF (Bit 13): Receive FIFO Full - Read Only. (0 = FIFO Not Full or 1 = FIFO Full)

DME (Bit 11): DMA Enable. (0 = DMA Disabled or 1 = DMA Enabled)

FIP (Bit 10–8): FIFO interrupt position. An interrupt is generated when FIP[2:0] + 1 words have been received in the FIFO. The interrupt is level-sensitive.

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					A		For current information contact Analog Devices at (781) 461-3881
		October 2000							ADSP-2192
				N		L
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			M			A
			I		C
	•	L						Note that PORST is not needed when using PCI or USB
			SMSelI(Bit 3): Stereo / Mono Select - AC’97 Mode
E				N				(and is shown as a no connect in Figure 8 on page 33); these
R			Only.H(0 = Mono Stream or 1 = Stereo Stream)
P			C			A		interfaces reset the DSP under their control as needed.
					T
	•ESLOT (Bits 7–4): AC’97 Slot Select - AC’97 Mode
T				A
				D
			Only.					DSP Software Reset

Table 26. AC’97 Slot Select Values

Slot	Mono	Stereo
0000–0010	Reserved
0011	Slot 3	Slots 3/4
0100	Slot 4	Slots 4/5
0101	Slot 5	Slots 5/6
0110	Slot 6	Slots 6/7
0111	Slot 7	Slots 7/8
1000	Slot 8	Slots 8/9
1001	Slot 9	Slots 9/10
1010	Slot 10	Slots 10/11
1011	Slot 11	Slots 11/12
1100	Slot 12	Not Allowed
1101–1111	Reserved

The DSP can generate a software reset using the RSTD bit in DSP Interrupt/Powerdown Registers). Generally, reset conditions are handled by forcing the DSPs to execute ROM- or RAM-based Reset Handler code. The Reset Han- dler that gets executed can be dictated by the Reset Source as defined by the CRST[1:0] bits in the Chip Mode/Status Register (CMSR).

The exact Reset Functionality is therefore defined by the ROM and RAM Reset Handler Code and as such is programmable.

Booting Modes

The ADSP-2192 has two mechanisms for automatically loading internal program memory after reset. The CRST pins, sampled during power on reset, implement these modes:

•Boot from PCI Host

•Boot from USB Host

Optionally, extra boot information can come from an SPI or Microwire serial EPROM during PCI or USB booting. The boot process flow appears in Figure 6 on page 32.

Power Management Description

The ADSP-2192 supports several states with distinct power management and functionality capabilities. These states encompass both hardware and software state.

The driver and DSP code take responsibility for detailed power management of the modem, so minimum power lev- els are achieved regardless of OS or BIOS. The driver and DSPs manage power by changing platform states as neces- sary in response to events.

Power Regulators

The ADSP-2192 is intended to operate in a variety of dif- ferent systems. These include PCI, CardBus, USB and imbedded (Sub-ISA) applications. The PCI and USB spec- ifications define power consumption limits that constrain the ADSP-2192 design.

2.5V Regulator Options

		In 5V and 3.3V PCI applications the ADSP-2192 2.5V
		IVDD supply will be generated by an on-chip regulator.
		The internal 2.5V supply (IVDD) can be generated by the
Soft Reset (RST in CMSR Register)		on-chip regulator combined with an external power transis-
		tor as shown in Figure 7 on page 32. To support the PCI
		specification’s power down modes, the two transistors con-
		trol the primary and auxiliary supply. If the reference							Y
The DSP has an internal power on reset circuit that resets								R
							A
		voltage on RVDD (typically the same as PCIVDD) drops
the DSP when power is applied. The DSP also has a Power					N				L
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		out, the VCTRLAUX will switch on the deviceMconnectedA
On Reset PORST signal that can initiate this master reset.			I				C
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		E					I
					N
		R		H
	This information applies to a product under development. Its characteristics and specifications are subjectPto change with-							A31
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	out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.						T
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