Analog Devices ADSP-2192

PRELIMINARY

TECHNICAL

DATA

PRELIMINARY

TECHNICAL

DATA

For current information contact Analog Devices at (781) 461-3881

ADSP-2192 October 2000

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

4REV. PrA

DSP Peripherals Architecture

Figure 1 on page 1 shows the DSP’s on-chip peripherals,

which include the Host port (PCI or USB), AC’97 port,

JTAG test and emulation port, flags, and interrupt

controller.

The ADSP-2192 can respond to up to thirteen interrupts at

any given time. A list of these interrupts appears in Table 1.

The AC’97 Codec port on the ADSP-2192 provides a com-

plete synchronous, full-duplex serial interface. This

interface completely supports the AC’97 standard.

The ADSP-2192 provides up to eight general-purpose I/O

pins, which are programmable as ei ther inputs or outputs.

These pins are dedicated general purpose Programmable

Flag pins.

The programmable interval timer generates periodic inter-

rupts. A 16-bit count register (TCOUNT) is decremented

every n cycles where n-1 is a scaling value stored in a 16-bit

reaches zero, an interrupt is generated and the count regis-

ter is reloaded from a 16-bit period register (TPERIOD).

Memory Architecture

The ADSP-2192 provides 140K words of on-chip SRAM

memory. This memory is divided into P rogram and Data

Memory blocks in each DSP’s memory map. In addi tion to

the internal memory space, the two cores can address two

additional and separate off-core memory spaces: I/O space

and shared memory space, as shown in Figure 3 on page 4.

The ADSP-2192’s two cores can access 80K and 48K loca-

tions that are accessible through two 24-bit address buses,

the PMA and DMA buses. The DSP uses slightly different

Figure 3. ADSP-2192 Internal/External Memory, Boot Memory, and I/O Memory Maps

SHARED RAM

(16x4K)

DATA RAM

BLOCK3

(16x16K)

DATA RAM

BLOCK2

(16x16K)

DATA RAM

BLOCK1

(16x16K)

RESERVED

0x00 0000

0x00 3FFF

0x00 4000

0x00 8000

0x00 C000

0x01 0000

0x01 4FFF

0x01 5000

0x01 FFFF

ADDRESS

DATA RAM

BLOCK0

(16x16K)

0x00 7FFF

0x00 BFFF

0x00 FFFF

PROGRAM RAM,

(24x16K)

PROGRAM ROM,

24x4K

0x01 3FFF

0x01 4000

0x02 0000

0x02 0FFF

DSP P0

MEMORY MAP

PAGE 2

PAGE 1

PAGE 0

SHARED

DSP I/O

MAPPED

REGISTERS

PAGES 0-255

(16x256)

0x00 00

0xFF FF

ADDRESS

SHARED RAM

(16x4K)

DATA RAM

BLOCK1

(16x16K)

RESERVED

0x00 0000

0x00 3FFF

0x00 4000

0x00 8000

0x01 0000

0x01 4FFF

0x01 5000

0x01 FFFF

ADDRESS

DATA RAM

BLOCK0

(16x16K)

0x00 7FFF

0x00 FFFF

PROGRAM RAM,

(24x16K)

PROGRAM ROM,

24x4K

0x01 3FFF

0x01 4000

0x02 0000

0x02 0FFF

DSP P1

MEMORY MAP

RESERVED

PAGE 2

PAGE 1

PAGE 0

SAME