Analog Devices ADSP-2192 ADSP-2192 October 2000

PRELIMINARY

TECHNICAL

DATA

PRELIMINARY

TECHNICAL

DATA

For current information contact Analog Devices at (781) 461-3881

ADSP-2192 October 2000

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

2REV. PrA

ADSP-219X DSP CORE FEATURES (CONTINUED)

• Single-Cycle Context Switch Between Two Sets of

Computational and DAG Registers

• Parallel Execution of Computation and Memory

Instructions

• Pipelined Architecture Supports Efficient Code Execu-

tion at Speeds up to 160 MIPS

• Register File Computations wi th All Non-conditional,

Non-parallel Computational Instructions

• Powerful Program Sequencer Provides Zero- Overhead

Looping and Conditional Instr uction Execution

• Architectural Enhancements for Compiled C/C++

Code Efficiency

• Architecture Enhancements Beyond ADSP-218x Fam-

ily are Supported with Instruction Set Extensions for

Added Registers, Ports, and Peripherals

ADSP-2192 DSP FEATURES (CONTINUED)

• Two ADSP-219x core processors (P0 and P1) on each

ADSP-2192 DSP chip

• 80K words of on-chip RAM on P0, configured as 64K

words on-chip 16-bit RAM for Data Memory and 16K

words on-chip 24-bit RAM for Program Memor y

• 48K words of on-chip RAM on P1, configured as 32K

words on-chip 16-bit RAM for Data Memory and 16K

words on-chip 24-bit RAM for Program Memor y

• 4K words of additional on-chip RAM shared by both

cores, configured as 4K words on-chip 16-bit RAM

• Flexible power management with selectable

power-down and idle modes

• Programmable PLL supports frequency multiplication,

enabling full-speed operation from low-speed input

clocks

• 2.5V internal operation supports 3.3V/5.0V

compliantI/O

• A Host port that supports either PCI (PCI interface

and CardBus) or USB (USB 1.1 compliant) interfaces;

both with DMA capability

• Sub-ISA Interface

• An AC’97 port supporting AC’97 Revision 2.1 compli-

ant interface for Exter nal Audio, Modem, and Handset

Codecs with DMA capability

• Eight dedicated general-purpos e I/O pins with inte-

grated interrupt support

• Each DSP core has a programmable 32-bit

interval timer

• Five DMA channels available on each core

• Boot methods include booting through PCI port, USB

port, or serial EEPROM

• JTAG Test Access Port supports on-chip emulation

and system debugging

• 144-lead LQFP package (20x20x1.4mm)

General note

This data sheet provides preliminary information for the

ADSP-2192 Digital Signal Processor.

GENERAL DESCRIPTION

The ADSP-2192 is a single-chip microcomputer optimized

for digital signal proce ssing (DSP) and other high speed

numeric processing applicat ions.

The ADSP-2192 combines the ADSP-219x family base

architecture (three computational units, two data address

generators and a program sequencer) into a chip with two

core processors. The ADSP-2192 includes a PCI-compati-

ble port, a USB-compatible port, an AC’97-compatible

port, a DMA controller, a programmable timer, general

purpose Programmable Flag pins, extensive interrupt capa-

bilities, and on-chip prog ram and data memory spaces.

The ADSP-2192 architecture is code compatible with

ADSP-218x family DSPs. Though the architectures are

compatible, the ADSP-2192 architecture has many

enhancements over the ADSP-218x architecture. The

enhancements to computational units, data address genera-

Figure 2. ADSP-219x DSP Core

INTERRUPT CONTROLLER/

TIMER/FLAGS

CACHE

64 x 24-BIT

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

ADSP-219x

DSP CORE

PROGRAM

SEQUENCER

DATA

FILE

MULT BARREL

SHIFTER ALU

INPUT

REGISTERS

RESULT

REGISTERS

16 x 16-BIT

CORE

INTERFACE

DAG1

4x4x16

DAG2

4x4x16