Analog Devices ADSP-2192 specifications 48K words of on-chip RAM on P1, configured as 32K

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				R			October 2000
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ADSP-2192					For current information contact Analog Devices at (781) 461-3881
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	L					• 48K words of on-chip RAM on P1, configured as 32K
ADSP-219X DSP CORE FEATURES (CONTINUED)
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		N				words on-chip 16-bit RAM for Data Memory and 16K
•RSingleH-Cycle Context Switch Between Two Sets of
P	C			A		words on-chip 24-bit RAM for Program Memory
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	ComputationalTand DAG Registers
	T	A				• 4K words of additional on-chip RAM shared by both
• ParallelDExecution of Computation and Memory

Instructions cores, configured as 4K words on-chip 16-bit RAM

•Pipelined Architecture Supports Efficient Code Execu- tion at Speeds up to 160 MIPS

•Register File Computations with All Non-conditional, Non-parallel Computational Instructions

•Powerful Program Sequencer Provides Zero- Overhead Looping and Conditional Instruction Execution

•Architectural Enhancements for Compiled C/C++ Code Efficiency

•Architecture Enhancements Beyond ADSP-218x Fam- ily are Supported with Instruction Set Extensions for Added Registers, Ports, and Peripherals

I N T ER RU PT CO NT R O LL ER /

TI M ER/ F LA G S

A D S P - 2 1 9 x

DS P C OR E

C A C H E

64 x 2 4 - BI T

D AG 1

D A G 2

PR O G R A M

4 x 4 x1 6

4x 4 x 1 6

SEQ U ENC E R

PM AD D RESS BU S

24

DM AD D R ESS BU S

24

PM D A T A B U S

24

B U S

C ON N E CT

DM DA T A BU S

16

( PX)

D AT A

C O R E

R EG I ST ER

IN T ERF A C E

FI L E

I N PU T

R EG I ST ERS

RESUL T

R EG I ST ERS

M U L T

B A RR EL

AL U

16 x 16 -B I T

SHI F T ER

Figure 2. ADSP-219x DSP Core

ADSP-2192 DSP FEATURES (CONTINUED)

•Flexible power management with selectable power-down and idle modes

•Programmable PLL supports frequency multiplication, enabling full-speed operation from low-speed input clocks

•2.5V internal operation supports 3.3V/5.0V compliant I/O

•A Host port that supports either PCI (PCI interface and CardBus) or USB (USB 1.1 compliant) interfaces; both with DMA capability

•Sub-ISA Interface

•An AC’97 port supporting AC’97 Revision 2.1 compli- ant interface for External Audio, Modem, and Handset Codecs with DMA capability

•Eight dedicated general-purpose I/O pins with inte- grated interrupt support

•Each DSP core has a programmable 32-bit interval timer

•Five DMA channels available on each core

•Boot methods include booting through PCI port, USB port, or serial EEPROM

•JTAG Test Access Port supports on-chip emulation and system debugging

•144-lead LQFP package (20x20x1.4mm)

General note

This data sheet provides preliminary information for the ADSP-2192 Digital Signal Processor.

GENERAL DESCRIPTION

The ADSP-2192 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.

The ADSP-2192 combines the ADSP-219x family base architecture (three computational units, two data address generators and a program sequencer) into a chip with two core processors. The ADSP-2192 includes a PCI-compati- ble port, a USB-compatible port, an AC’97-compatible port, a DMA controller, a programmable timer, general purpose Programmable Flag pins, extensive interrupt capa- bilities, and on-chip program and data memory spaces.

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Two ADSP-219x core processors (P0 and P1) on each	The ADSP-2192 architecture is code compatible with
ADSP-2192 DSP chip
	ADSP-218x family DSPs. Though the architectures are
80K words of on-chip RAM on P0, configured as 64K
	compatible, the ADSP-2192 architecture has many						Y
words on-chip 16-bit RAM for Data Memory and 16K	enhancements over the ADSP-218x architecture. The
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words on-chip 24-bit RAM for Program Memory					A
	enhancements to computational units, data address generaN-						L
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This information applies to a product under development. Its characteristics and specifications are subject to changePwith-			CREV. PrA A
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.		E			T
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