Analog Devices ADSP-2192 specifications - page 8

PRELIMINARY
TECHNICAL
DATA
PRELIMINARY
TECHNICAL
DATA
For current information contact Analog Devices at (781) 461-3881
ADSP-2192 October 2000
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
8REV. PrA
DSP Core Register Space
Each DSP has an internal register that is accessible with no
latency. These registers are accessible only from within the
DSP, using the REG() instruction.
Peripheral Device Control Register Space
This Register Space is accessible by both DSPs, the PCI,
Sub-ISA, and USB Buses. Note that certai n sections of this
space are exclusive to either the PCI, USB, or Sub-ISA
Buses. These registers control the operation of the periph-
erals of the ADSP-2192. The DSP accesses these registers
using the IO() instruction.
USB Register Space
These registers control the operation and configuration of
the USB Interface. Most of these registers are only accessi-
ble via the USB Bus, although a subset is accessible to the
DSP.
Card Bus interface
The ADSP-2192’s PC Card Bus interface meets the state
and timing specifications def ined for PCMCIA’s PC Card
Bus Standard April 1998 Release 6.1. It supports up to
three card functions. Multiple function PC cards require a
separate set of Configuration registers per function. A pri-
mary Card Information Structure common to all functions
is required. Separate secondary Card Information Struc-
tures, one per function, are also required. Data for each CIS
is loaded by the DSP during bootstrap loading.
The host PC can read the CIS data at any time. If needed,
the WAIT control can be activated to extend the read oper-
ation to meet bus write access to the CIS data.
Using the PCI Interface
The ADSP-2192 includes a 33-Mhz, 32-bit PCI interface
to provide control and data paths between the part and the
host CPU. The PCI interface is compliant with the PCI
Local Bus Specification Revision 2.2. The interface sup-
ports both bus mastering as wel l as bus target interfaces.
The PCI Bus Power Management Interface Specification
Revision 1.1 is supported and additional features as needed
by PCI designs are included.
Tar ge t/ Sl a ve In te r fa ce
The ADSP-2192 PCI interface contains three separate
functions, each with its own configuration space. Each
function contains four base address registers used to access
ADSP-2192 control registers and DSP memory. Base
Address Register (BAR) 1 is used to point to the control
registers. The addresses specified in these tables are offsets
from BAR1 in each of the functions. PCI memory-type
accesses are used to read and write the registers.
DSP memory accesses use BAR2 or BAR3 of each func-
tion. BAR2 is used to access 24-bit DSP memory; BAR3
accesses 16-bit DSP memory. Maps of the BAR2 and
BAR3 registers appear in Table 8 on page 14 and Table 9
on page 15.
The lower half of the allocated space pointed to by each
DSP memory BAR is the DSP memory for DSP c ore P0.
The upper half is the memory space associated with DSP
core P1. PCI transactions to and from DSP memory use the
DMA function within the DSP core. Thus each word trans-
ferred to or from PCI space uses a single DSP clock cycle to
perform the internal DSP data transfer. Byte-wide accesses
to DSP memory ar e not suppor ted.
I/O type accesses are supported via BAR4. Both the control
registers accessible via BAR1 and the DSP memory acces-
sible via BAR2 and BAR3 can be accessed wi th I/O
accesses. Indirect access is used to read and write both the
control registers and the DSP memory. For the control reg-
ister accesses, a address register points to the word to be
accessed while a separate register is used to transfer the
data. Read/write control is pa rt of the address reg ister. Only
16-bit accesses are possible via the I/O space.
A separate set of registers is used to perform the same func-
tion for DSP memory access. Control for these accesses
includes a 24-bit/16-bit select as well as direction control.
The data register for DSP memory accesses is a full 24-bits
wide. 16-bit accesses will be loaded into the lower 16-bits of
the register. Table 10 on page 17 lists the registers directly
accessible from BAR4.
Bus Master Interface
As a bus master, the PCI interface can transfer DMA data
between system memory and the DSP. The control registers
for these transfers are available both to the host and to the
DSPs. Four channels of bus-mastering DMA are supported
on the ADSP-2192.
Two channels are associated with the receive data and two
are associated with the transmit data. The internal DSPs
will typically control initiation of bus master transactions.
DMA host bus master transfers can specify either standard
circular buffers in system memory or perform scatter-gather
DMA to host memory.
Each bus master DMA channel includes 4 registers to spec-
ify a standard circular buffer in system memory. The Base
Address points to the start of the circular buffer. The Cur-
rent Address is a pointer to the current position within that
buffer. The Base Count specifies the size of the buffer in
bytes, while the Current Count keeps track of how many
bytes need to be transferred before the end of the buffer is
reached. When the end of the buffer is reached, the channel
can be programmed to loop back to the begi nning and con-
tinue the transfers. When this looping occurs, a Status bit
will be set in the DMA Control Register.