CREV. PrA a | Analog Devices ADSP-2192 specs

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														R																					October 2000
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	ADSP-2192																For current information contact Analog Devices at (781) 461-3881
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			L										C			Table 38. 144-Lead LQFP								Table 39. 144-Lead LQFP										Table 39. 144-Lead LQFP
	Table 38. 144-Lead LQFP															Table 38. 144-Lead LQFP								Table 39. 144-Lead LQFP										Table 39. 144-Lead LQFP
			E										I			Pins By Signal								Pins By Pin # (Continued)										Pins By Pin # (Continued)
	Pins By SignalN															Pins By Signal								Pins By Pin # (Continued)										Pins By Pin # (Continued)
	R									H
P							C							A
							C							A
			E										T				SIGNAL					PIN #			SIGNAL							PIN #			SIGNAL		PIN #
		SIGNALT										A PIN #					SIGNAL					PIN #			SIGNAL							PIN #			SIGNAL		PIN #
											D

		PCIVDD												18								79										23			AD4		53
		PCIVDD												18			TRST					79			TRDY							23			AD4		53

		PCIVDD												29			XTALI					118										24			AD3		54
		PCIVDD												29			XTALI					118			DEVSEL							24			AD3		54

		PCIVDD												38			XTALO					119										25			AD2		55
		PCIVDD												38			XTALO					119			STOP							25			AD2		55

		PCIVDD												51																		26			AD1		56
		PCIVDD												51		Table 39 lists the LQFP									CLKRUN							26			AD1		56
																Table 39 lists the LQFP
		PCIVDD												132		pinout by pin number.																27			AD0		57
		PCIVDD												132		pinout by pin number.									PERR							27			AD0		57

		PCIVDD												144		Table 39. 144-Lead LQFP																28			IVDD		58
		PCIVDD												144		Table 39. 144-Lead LQFP									SERR							28			IVDD		58
																Pins By Pin #
														27		Pins By Pin #									PCIVDD							29			IGND		59
		PERR												27											PCIVDD							29			IGND		59
																	SIGNAL					PIN #

		PME												135											PCIGND							30			RVAUX		60
		PME												135											PCIGND							30			RVAUX		60

																	PCIGND					1
														121
		PORST																							PAR							31			CTRLAUX		61
		PORST																							PAR							31			CTRLAUX		61
																	AD25					2

		REQ												134											CBE1							32			IVDD		62
		REQ												134											CBE1							32			IVDD		62
																	AD24					3
														129
		RST																							AD15							33			CTRLVDD		63
		RST																							AD15							33			CTRLVDD		63
																						4

		RVAUX												60			CBE3								AD14							34			RVDD		64
		RVAUX												60											AD14							34			RVDD		64

																	IDSEL					5
		RVDD												64			IDSEL					5			AD13							35			AVDD		65
		RVDD												64											AD13							35			AVDD		65

																	AD23					6
		SCK												72			AD23					6			AD12							36			NC		66
		SCK												72											AD12							36			NC		66

																	AD22					7
		SDA												71			AD22					7			AD11							37			AGND		67
		SDA												71											AD11							37			AGND		67

																	AD21					8
		SDI0												99			AD21					8			PCIVDD							38			AQGND		68
		SDI0												99											PCIVDD							38			AQGND		68

																	PCIVDD					9
		SDI1												98			PCIVDD					9			PCIGND							39			NC		69
		SDI1												98											PCIGND							39			NC		69

																	PCIGND					10
		SDI2												97			PCIGND					10			IVDD							40			NC		70
		SDI2												97											IVDD							40			NC		70

																	AD20					11
		SDO												100			AD20					11			IGND							41			SDA		71
		SDO												100											IGND							41			SDA		71

																	AD19					12
		SEN												73			AD19					12			AD10							42			SCK		72
		SEN												73											AD10							42			SCK		72

																	AD18					13
														28
		SERR																							AD9							43			SEN		73
		SERR																							AD9							43			SEN		73
																	AD17					14

		STOP												25											AD8							44			EMU		74
		STOP												25											AD8							44			EMU		74
																	AD16					15
		SYNC												101																		45
																									CBE0										TMS		75
																									CBE0										TMS		75
																						16

		TCK												78			CBE2								AD7							46			IOGND		76
		TCK												78											AD7							46			IOGND		76

																						17

		TDI												80			FRAME								AD6							47			IOVDD		77
		TDI												80											AD6							47			IOVDD		77

																	PCIVDD					18
		TDO												81			PCIVDD					18			AD5							48			TCK		78
		TDO												81											AD5							48			TCK		78

																	IVDD					19
		TMS												75											IVDD							49					79
																																			TRST
																																			TRST
																	IGND					20
														23											IGND							50			TDI		80
		TRDY
		TRDY
																	PCIGND					21
																	PCIGND					21			PCIVDD							51			TDO		81			Y
																									PCIVDD							51			TDO		81


																						22																		R
																	IRDY																							R
																	IRDY								PCIGND							52			IO0		82		A
																									PCIGND							52			IO0		82	IN		L
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																																					M			A
																																					I		C
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48																																				R	H
48										This information applies to a product under development. Its characteristics and specifications are subject to changePwith-																											CREV. PrA A
										out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. E																													T
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Analog Devices ADSP-2192 specifications CREV. PrA a

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.

Contents

Preliminary Technical Data 48K words of on-chip RAM on P1, configured as 32K Words on-chip 16-bit RAM for Data Memory and 16K REV. PrA Programmable interval timer generates periodic inter Rupts. a 16-bit count register Tcount is decremented DSP-DSP Output DSP-DSP Semaphore DSP-DSP Interrupt Loop stack interrupt enable ADSP-2192 Industry standard AC’97 serial interface AC-Link ADSP-2192 includes a 33MHz, 32 bit bus master PCIPliant codecs to the ADSP-2192. The ACLink implements Ification. This interface supports the high data rates DSP memory accesses use BAR2 or BAR3 of each func Tion. BAR2 is used to access 24-bit DSP memory BAR3DSP, using the REG instruction BAR3 registers appear in on page 14 and Table Mode the functions of the registers are mapped as follows Rpci Dmah controller can be programmed to perform scatADSP-2192 without processor intervention. In scat Transmit Channel 0 Bus Master Transactions Tx0 DMA Channel Interrupt Target accessesI to registers and DSP memory can go RthroughHany function. As long as the Memory Space accessRegister or memory location within the ADSP-2192. Simi Bist Data Word. BAR3 Mode is typically used for Data Memory Inta PCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Unused Reserved A15 7FFC 9FFC 0x0-0x3 DSP Memory Buffer Base Addr 0x4-0x5 DSP Memory Buffer Size0x6-0x7 DSP Memory Buffer RD Offset 0x8-0x9 DSP Memory Buffer WR Offset EP5 EP6EP7 EP8 Descriptor command is contained in this register. Release Number returned in the GET DeviceRelease Number is 0x0100, which corresponds to Device-specific attributes returned in the GET USB EP4 NAK USB EP5 NAKUSB EP6 NAK USB EP7 NAK A21 ISE = Current interrupt is for a Setup token INT = Active interrupt for the 8052 MCUThisR registerHprovides information as the total size Fixed Endpoints Control Endpoint 0x01 0x02 0x00 ADIREV. PrA A23 USB Mcucode XXX USB Regio BRequest 0xA0WValue L Address WValue H A27 If for some reason the host sends more data than the max Packetsize, theNUSB core accepts it, as long as there isSufficientCroom in theAFIFO Power themselves and the ADSP-2192 completely down Deassertion of PDW1 high causes a wake-up of the DSPAn active lowIRST input to be derived from PCI RST Pmeen output from the Combo Master should Fifo SMSelIBit 3 Stereo / Mono Select AC’97 Mode Interfaces reset the DSP under their control as neededEslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only Is shown as a no connect in on page 33 these ADSP-2192 Boot Process Flow ADSP-2192 can be clocked by a crystal oscillator. If a ForEthis configuration.T Manufacturer.I a parallel-resonant, fundamental frequencyRmicroprocessorH -grade 24.576 MHz crystal should be used Tion-level simulator a C/C++ compiler and a C/C++ Run-time library that includes DSP and mathematical func A35 AD0 AD1AD2 AD3 CBE0 CBE1 CBE2 CBE3 CLK 130Clkrun Devsel Frame GNT Idsel Intab 131 128 PCI / ISA Interrupt Irdy PARPcignd Pcivdd Emulator Event Pin Emulator Clock Input Emulator Data Input Emulator Mode Select Emulator Logic ResetEmulator Data Output Acvaux Aiognd Avdd Ctrlaux Ctrlvdd IgndIvdd Rvaux Rvdd Specifications are subject to change TBD Supply Current Dynamic @ 160 Mips Internal Supply Current IdleInput Capacitance6 FIN=1 MHz VIN=2.5V AEN Setup to IOR / IOW Falling Address Setup to IOR / IOW FallingWrite Data Setup to IOW Rising IOR / IOW Strobe Width 100 Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide