Irdy, Par, Pcignd, Pcivdd, Perr, Pme | Analog Devices ADSP-2192

Y

R

A

ADSP-2192

For current information contact Analog Devices at (781) 461-3881

N

L

I

M

A

I

C

L

Table 28. ADSP-2192 Pin Configurations: PCI/USB Bus Interface (Continued)

E

I

N

R

H

P

ALQFP

I/O

Description

Pin NameC

E

T

T

A

IRDY

D

22

I/O

PCI Initiator Ready

PAR

31

I/O

PCI Bus Parity/

PCIGND

1, 10,

I

PCI Ground

21, 30,

39, 52,

133

PCIVDD

9, 18,

I

PCI Vdd supply

29, 38,

51,

132,

144

27

I/O

PCI Parity Error/ USB- (Inverting input)

PERR

135

O

PCI Power Management Event

PME

134

O

Request

REQ

129

I

PCI Reset

RST

28

O

PCI System Error/ USB+ (Non-inverting input).-5-

SERR

25

I/O

PCI Target Stop

STOP

23

I/O

PCI Target Ready

TRDY

October 2000

Table 29. Pin Configurations: Crystal / Configuration Pins

Pin Name

LQFP

I/O

Description

BUS0

124

I

PCI/ Sub-ISA /CardBus Select pins

BUS1

123

I

PCI/ Sub-ISA /CardBus Select pins

CLKSEL

116

I/O

Clock Select

IGND

122

I

IGND

NC

127

O

No Connect

121

I

Power On Reset

PORST

XTALI

118

I

Crystal input pin (24.576MHz)

XTALO

119

I/O

Crystal output pin

Table 30. Pin Configurations: Analog Pins

Pin Name

LQFP

I/O

Description

AGND

67

I

Analog Ground

Y

AQGND

68

I

Reference Analog Ground

R

A

N

L

I

I

CTRLAUX

61

I

X supply

A

M

L

C

E

I

N

38

R

H

This information applies to a product under development. Its characteristics and specifications are subject to changePwith-

CREV. PrA A

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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T

A

T

D

Image 38

Analog Devices ADSP-2192 Irdy, Par, Pcignd, Pcivdd, Perr, Pme, Req, Serr, Stop, Trdy, BUS0, BUS1, Clksel, Ignd, Xtalo

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.

Contents

Preliminary Technical Data 48K words of on-chip RAM on P1, configured as 32K Words on-chip 16-bit RAM for Data Memory and 16K REV. PrA Programmable interval timer generates periodic inter Rupts. a 16-bit count register Tcount is decremented DSP-DSP Output DSP-DSP Semaphore DSP-DSP Interrupt Loop stack interrupt enable ADSP-2192 Pliant codecs to the ADSP-2192. The ACLink implements Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Ification. This interface supports the high data rates DSP, using the REG instruction DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 BAR3 registers appear in on page 14 and Table ADSP-2192 without processor intervention. In scat Mode the functions of the registers are mapped as followsRpci Dmah controller can be programmed to perform scat Transmit Channel 0 Bus Master Transactions Tx0 DMA Channel Interrupt Register or memory location within the ADSP-2192. Simi Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access Bist Data Word. BAR3 Mode is typically used for Data Memory Inta PCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Unused Reserved A15 7FFC 9FFC 0x6-0x7 DSP Memory Buffer RD Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x8-0x9 DSP Memory Buffer WR Offset EP7 EP5EP6 EP8 Release Number is 0x0100, which corresponds to Descriptor command is contained in this register.Release Number returned in the GET Device Device-specific attributes returned in the GET USB EP6 NAK USB EP4 NAKUSB EP5 NAK USB EP7 NAK A21 ThisR registerHprovides information as the total size ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU Fixed Endpoints Control Endpoint REV. PrA A23 0x01 0x02 0x00ADI USB Mcucode XXX WValue L USB RegioBRequest 0xA0 Address WValue H A27 SufficientCroom in theAFIFO If for some reason the host sends more data than the maxPacketsize, theNUSB core accepts it, as long as there is An active lowIRST input to be derived from PCI RST Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP Pmeen output from the Combo Master should Fifo Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Is shown as a no connect in on page 33 these ADSP-2192 Boot Process Flow ADSP-2192 can be clocked by a crystal oscillator. If a RmicroprocessorH -grade 24.576 MHz crystal should be used ForEthis configuration.TManufacturer.I a parallel-resonant, fundamental frequency Tion-level simulator a C/C++ compiler and a C/C++ Run-time library that includes DSP and mathematical func A35 AD2 AD0AD1 AD3 Clkrun Devsel Frame GNT Idsel Intab CBE0 CBE1 CBE2 CBE3 CLK130 131 128 PCI / ISA Interrupt Pcignd IrdyPAR Pcivdd Emulator Event Pin Emulator Clock Input Emulator Data Input Emulator Data Output Emulator Mode SelectEmulator Logic Reset Ivdd Rvaux Rvdd Acvaux Aiognd AvddCtrlaux Ctrlvdd Ignd Specifications are subject to change TBD Input Capacitance6 FIN=1 MHz Supply Current Dynamic @ 160 Mips InternalSupply Current Idle VIN=2.5V Write Data Setup to IOW Rising AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling IOR / IOW Strobe Width 100 Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide