Analog Devices ADSP-2192

PRELIMINARY

TECHNICAL

DATA

PRELIMINARY

TECHNICAL

DATA

For current information contact Analog Devices at (781) 461-3881

ADSP-2192 October 2000

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

6REV. PrA

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially.

Interrupts can be masked or unmasked with the IMASK

with the bits in IMASK; the highest priority unmasked

interrupt is then sele cted. The emulation, power down, and

reset interrupts are nonmaskable with the IMASK register,

but software can use the DIS INT instruction to mask the

power down interrupt.

The IRPTL register is used to force and clear interrupts.

On-chip stacks preserve the processor status and are auto-

matically maintained during interrupt handling. To support

interrupt, loop, and subroutine nesting, the PC stack is

33-levels deep, the loop stack is eight-levels deep, and the

status stack is sixteen-levels deep. To prevent stack overflow,

the PC stack can generate a stack level interrupt if the PC

stack falls below 3 locations full or rises above 28

locationsfull.

The following instructions globally enable or disable inter-

rupt servicing, regardless of the state of IMASK.

ENA INT;

DIS INT;

At reset, interrupt servicing is disabled.

For quick servicing of interrupts, a secondary set of DAG

and computational registers exist. Switching between the

primary and secondary registers lets programs quickly ser-

vice interrupts, while preserving the DSP’s state.

DMA Controller

The ADSP-2192 has a DMA controller that supports auto-

mated data transfers with minimal overhead for the DSP

core. Cycle stealing DMA transfers can occur between the

ADSP-2192’s internal memory and any of its DMA capable

peripherals. Additionally, DMA transfers can also be

accomplished between any of the DMA capable peripher-

als. DMA capable peripherals include the PCI and AC’97

ports. Each individual DMA capable peripheral has a dedi-

cated DMA channel. DMA sequences do not contend for

bus access with the DSP core; instead, DMAs “steal” cycles

to access memory.

All DMA transfers use the Program Memory (PMA/PMD)

buses shown in Figure 1 on page 1.

External Interfaces

There are several different interfaces supported on the

ADSP-2192. These include both internal and external

interfaces. The three separate PCI configuration spaces are

programmable to set up the device in various Plug-and-Play

configurations.

The ADSP-2192 provides the following types of external

interfaces: PCI, USB, Sub-ISA, CardBus, AC’97, and

serial EEPROM. The following sections discuss those

interfaces.

3 Reserved

4 Reserved

5 Reserved

6 Reserved

7 Output Register Bus Lock

8InputDSP-DSP Semaphore 00

9InputDSP-DSP Semaphore 11

10 Input DSP-DSP Interrupt 2

11 Input Reserved

12 Input AC’97 Register - PDC Bus

Access Status 4

13 Input PDC Interface Busy Status

(write from DSP pending) 5

14 Input Reserved

15 Input Register Bus Lock Status 7

Table 3. Interrupt Control (ICNTL) register bits

Bit Description

0–3 Reserved

4 Interrupt nesting enable

5 Global interrupt enable

6 Reserved

7 MAC biased rounding enable

8–9 Reserved

10 PC stack interrupt enable

Table 2. DSP-to-DSP Semaphores Register Table

Flag

Bit

Direct-

ion Function

DSP

Core

Flag

11 Loop stack interrupt enable

12 Low power idle enable

13–15 Reserved

Table 3. Interrupt Control (ICNTL) register bits

Bit Description