PRELIMINARY
TECHNICAL
DATA
PRELIMINARY
TECHNICAL
DATA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 9REV. PrA
For current information contact Analog Devices at (781) 461-3881 ADSP-2192October 2000
When transferring samples to and from DSP memory, the
PCI DMA controller can be programmed to perform scat-
ter-gather DMA. This mode allows the data to be split up
in memory, and yet be able to be transferred to and from the
ADSP-2192 without processor intervention. In scat-
ter-gather mode, the DMA controller can read the memory
address and word count from an array of buffer descriptors
called the Scatter-Gather Descriptor (SGD) table. This
allows the DMA engine to sustain DMA transfers until all
buffers in the SGD table are transferred.
To initiate a scatter-gather transfer between memory and
the ADSP-2192, the following steps are involved:
1. Software driver prepares a SGD table in system mem-
ory. Each descriptor is eight bytes long and consists of
an address pointer to the starting address and the trans-
fer count of the memory buffer to be transferred. In any
given SGD table, two consecutive SGDs are offset by
eight bytes and are aligned on a 4-byte boundary. Each
SGD contains:
a. Memory Address (Buffer Start) – 4 bytes
b. Byte Count (Buffer Size) – 3 bytes
c. End of Linked List (EOL) – 1 bit (MSBit)
d. Flag – 1 bit (MSBit – 1)
2. Initialize DMA control registers with transfer specific
information such as number of total bytes to transfer,
direction of transfer, etc.
3. Software driver initializes the hardware pointer to the
SGD table.
4. Engage scatter-gather DMA by writ ing the start value
to the PCI channel Control/Status register.
5. The ADSP-2192 will then pull in samples as pointed to
by the descriptors as needed by the DMA engine.
When the EOL is reached, a status bit will be set and
the DMA will end if the data buffer is not to be looped.
If looping is to occur, DMA transfers will continue
from the beginning of the table until the channel is
turned off.
6. Bits in the PCI Control/Status register control whether
an interrupt occurs when the EOL is reached or when
the FLAG bit is set.
Scatter-gather DMA uses four registers. In scatter-gather
mode the functions of the registers are mapped as follows:
In either mode of operation, inte rrupts can be generated
based upon the total number of bytes transferred. Each
channel has two 24-bit registers to count the bytes trans-
ferred and generate interr upts as appropriate. The
Interrupt Base Count register specifies the number of bytes
to transfer prior to generating an interrupt. The Interrupt
Count register specifies the current number left prior to
generating the interrupt. When the Interrupt Count register
reaches zero, a PCI interrupt can be generated. Addition-
ally, the Interrupt Count register will be reloaded from the
Interrupt Base Count and conti nue counting down for the
next interrupt.
PCI Interrupts
There are a variety of potential sources of interrupts to the
PCI host besides the bus master DMA interrupts. A single
interrupt pin, INTA is used to signal these interrupts back
to the host. The PCI Interrupt Register consolidates all of
the possible interrupt sources; the bits of this register are
shown in Table 5 on page 9. The register bits are s et by the
various sources, and can be cleared by writing a 1 to the
bit(s) to be cleared.
PCI Control Register.
This register must be initialized by the DSP ROM code
prior to PCI enumeration. (It has no effect in ISA or USB
mode.) Once the Configuration Ready bit has been set to 1,
the PCI Control Register becomes read-only, and further
access by the DSP to configuration space is disallowed. The
bigs of this register are shown in Table6 on page 10.
Table 4. Register-Mapping in Scatter-Gather Mode
Standard Circular Buffer
Mode
Scatter-Gather Mode
Function
Base Address SGD Table Pointer
Current Address SGD Current Pointer
Address
Base Count SGD Pointer
Current Count Current SGD Count
Table 5. PCI Interrupt Register
Bit Name Comments
0 Reserved Reserved
1 Rx0 DMA Channel Interrupt Receive Channel 0 Bus Master Transactions
2 Rx1 DMA Channel Interrupt Receive Channel 1 Bus Master Transactions