Analog Devices ADSP-2192 specifications Mode the functions of the registers are mapped as follows

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For current information contact Analog Devices at (781) 461-3881

ADSP-2192

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October 2000

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samples to and from DSP memory, the

Scatter-gather DMA uses four registers. In scatter-gather

When transferringI

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mode the functions of the registers are mapped as follows:

RPCI DMAH controller can be programmed to perform scat-

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terE-gather DMA.T This mode allows the data to be split up

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Table 4. Register-Mapping in Scatter-Gather Mode

in memory,D and yet be able to be transferred to and from the

ADSP-2192 without processor intervention. In scat-

Standard Circular Buffer

Scatter-Gather Mode

ter-gather mode, the DMA controller can read the memory

address and word count from an array of buffer descriptors

Mode

Function

called the Scatter-Gather Descriptor (SGD) table. This

Base Address

SGD Table Pointer

allows the DMA engine to sustain DMA transfers until all

buffers in the SGD table are transferred.

Current Address

SGD Current Pointer

To initiate a scatter-gather transfer between memory and

Address

the ADSP-2192, the following steps are involved:

Base Count

SGD Pointer

1.

Software driver prepares a SGD table in system mem-

ory. Each descriptor is eight bytes long and consists of

Current Count

Current SGD Count

an address pointer to the starting address and the trans-

fer count of the memory buffer to be transferred. In any

In either mode of operation, interrupts can be generated

given SGD table, two consecutive SGDs are offset by

based upon the total number of bytes transferred. Each

eight bytes and are aligned on a 4-byte boundary. Each

channel has two 24-bit registers to count the bytes trans-

SGD contains:

ferred and generate interrupts as appropriate. The

a. Memory Address (Buffer Start) – 4 bytes

Interrupt Base Count register specifies the number of bytes

b.

Byte Count (Buffer Size) – 3 bytes

to transfer prior to generating an interrupt. The Interrupt

c.

End of Linked List (EOL) – 1 bit (MSBit)

Count register specifies the current number left prior to

generating the interrupt. When the Interrupt Count register

d. Flag – 1 bit (MSBit – 1)

reaches zero, a PCI interrupt can be generated. Addition-

2.

Initialize DMA control registers with transfer specific

ally, the Interrupt Count register will be reloaded from the

information such as number of total bytes to transfer,

Interrupt Base Count and continue counting down for the

direction of transfer, etc.

next interrupt.

3.

Software driver initializes the hardware pointer to the

PCI Interrupts

SGD table.

There are a variety of potential sources of interrupts to the

4.

Engage scatter-gather DMA by writing the start value

PCI host besides the bus master DMA interrupts. A single

to the PCI channel Control/Status register.

interrupt pin, INTA is used to signal these interrupts back

5.

The ADSP-2192 will then pull in samples as pointed to

to the host. The PCI Interrupt Register consolidates all of

by the descriptors as needed by the DMA engine.

the possible interrupt sources; the bits of this register are

When the EOL is reached, a status bit will be set and

shown in Table 5 on page 9. The register bits are set by the

the DMA will end if the data buffer is not to be looped.

various sources, and can be cleared by writing a 1 to the

If looping is to occur, DMA transfers will continue

bit(s) to be cleared.

from the beginning of the table until the channel is

turned off.

PCI Control Register.

6. Bits in the PCI Control/Status register control whether

This register must be initialized by the DSP ROM code

an interrupt occurs when the EOL is reached or when

prior to PCI enumeration. (It has no effect in ISA or USB

the FLAG bit is set.

mode.) Once the Configuration Ready bit has been set to 1,

the PCI Control Register becomes read-only, and further

access by the DSP to configuration space is disallowed. The

bigs of this register are shown in Table 6 on page 10.

Table 5. PCI Interrupt Register

Bit

Name

Comments

0

Reserved

Reserved

1

Rx0 DMA Channel Interrupt

Receive Channel 0 Bus Master Transactions

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2

Rx1 DMA Channel Interrupt

Receive Channel 1 Bus Master Transactions

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REV. PrA

This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

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