7FFC, 9FFC | Analog Devices ADSP-2192 instruction

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October 2000

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ADSP-2192

For current information contact Analog Devices at (781) 461-3881

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Table 9. 16-bit PCI DSP Memory Map (BAR 3 Mode) (Continued)

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PBlock

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Byte3

Byte2

Byte1

Byte0

Offset

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D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0001

8000

DSP P0 DataDRAM Block 3

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0001

8004

:

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0001 FFFC

DSP P0 Program RAM Block

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0002

0000

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0002

0004

:

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0002

7FFC

DSP P0 Program ROM Block

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0002

8000

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0002

8004

:

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0002

9FFC

Reserved Space

RESERVED

RESERVED

RESERVED

RESERVED

0x0002 A000

:

RESERVED

RESERVED

RESERVED

RESERVED

0x0003 FFFC

DSP P1 Data RAM Block 0

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0004

0000

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0004

0004

:

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0004

7FFC

DSP P1 Data RAM Block 1

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0004

8000

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0004

8004

:

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0004 FFFC

Reserved Space.

RESERVED

RESERVED

RESERVED

RESERVED

0x0005

0000

:

RESERVED

RESERVED

RESERVED

RESERVED

0x0005 FFFC

DSP P1 Program RAM Block

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0006

0000

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0006

0004

:

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0006

7FFC

DSP P1 Program ROM Block

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0006

8000

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0006

8004

:

D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0006

9FFC

Reserved Space

RESERVED

RESERVED

RESERVED

RESERVED

0x0006 A000

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RESERVED

RESERVED

RESERVED

RESERVED

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0x0007 FFFCM

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16

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This information applies to a product under development. Its characteristics and specifications are subject to changePwith-

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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Image 16

Analog Devices ADSP-2192 specifications 7FFC, 9FFC

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.

Contents

Preliminary Technical Data 48K words of on-chip RAM on P1, configured as 32K Words on-chip 16-bit RAM for Data Memory and 16K REV. PrA Programmable interval timer generates periodic inter Rupts. a 16-bit count register Tcount is decremented DSP-DSP Output DSP-DSP Semaphore DSP-DSP Interrupt Loop stack interrupt enable ADSP-2192 Industry standard AC’97 serial interface AC-Link ADSP-2192 includes a 33MHz, 32 bit bus master PCIPliant codecs to the ADSP-2192. The ACLink implements Ification. This interface supports the high data rates DSP memory accesses use BAR2 or BAR3 of each func Tion. BAR2 is used to access 24-bit DSP memory BAR3DSP, using the REG instruction BAR3 registers appear in on page 14 and Table Rpci Dmah controller can be programmed to perform scat Mode the functions of the registers are mapped as followsADSP-2192 without processor intervention. In scat Transmit Channel 0 Bus Master Transactions Tx0 DMA Channel Interrupt Target accessesI to registers and DSP memory can go RthroughHany function. As long as the Memory Space accessRegister or memory location within the ADSP-2192. Simi Bist Data Word. BAR3 Mode is typically used for Data Memory Inta PCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Unused Reserved A15 7FFC 9FFC 0x0-0x3 DSP Memory Buffer Base Addr 0x4-0x5 DSP Memory Buffer Size0x6-0x7 DSP Memory Buffer RD Offset 0x8-0x9 DSP Memory Buffer WR Offset EP5 EP6EP7 EP8 Descriptor command is contained in this register. Release Number returned in the GET DeviceRelease Number is 0x0100, which corresponds to Device-specific attributes returned in the GET USB EP4 NAK USB EP5 NAKUSB EP6 NAK USB EP7 NAK A21 ISE = Current interrupt is for a Setup token INT = Active interrupt for the 8052 MCUThisR registerHprovides information as the total size Fixed Endpoints Control Endpoint ADI 0x01 0x02 0x00REV. PrA A23 USB Mcucode XXX USB Regio BRequest 0xA0WValue L Address WValue H A27 Packetsize, theNUSB core accepts it, as long as there is If for some reason the host sends more data than the maxSufficientCroom in theAFIFO Power themselves and the ADSP-2192 completely down Deassertion of PDW1 high causes a wake-up of the DSPAn active lowIRST input to be derived from PCI RST Pmeen output from the Combo Master should Fifo SMSelIBit 3 Stereo / Mono Select AC’97 Mode Interfaces reset the DSP under their control as neededEslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only Is shown as a no connect in on page 33 these ADSP-2192 Boot Process Flow ADSP-2192 can be clocked by a crystal oscillator. If a Manufacturer.I a parallel-resonant, fundamental frequency ForEthis configuration.TRmicroprocessorH -grade 24.576 MHz crystal should be used Tion-level simulator a C/C++ compiler and a C/C++ Run-time library that includes DSP and mathematical func A35 AD0 AD1AD2 AD3 CBE0 CBE1 CBE2 CBE3 CLK 130Clkrun Devsel Frame GNT Idsel Intab 131 128 PCI / ISA Interrupt Irdy PARPcignd Pcivdd Emulator Event Pin Emulator Clock Input Emulator Data Input Emulator Logic Reset Emulator Mode SelectEmulator Data Output Ctrlaux Ctrlvdd Ignd Acvaux Aiognd AvddIvdd Rvaux Rvdd Specifications are subject to change TBD Supply Current Dynamic @ 160 Mips Internal Supply Current IdleInput Capacitance6 FIN=1 MHz VIN=2.5V AEN Setup to IOR / IOW Falling Address Setup to IOR / IOW FallingWrite Data Setup to IOW Rising IOR / IOW Strobe Width 100 Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide