User Manual version 2207
uSDRAM/VCM CAS LATENCY
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing.
The Choice: 2, 3 or SPD
uSDRCLK CONTROL
This item controls the phase of SDRCLK that lags behind
SDCLK.
The choice: Enabled or Disabled.
uSDWCLK CONTROL CS#/CKE
This item controls the phase of SDWCLK used for chip set select signals pin that lags ahead SDCLK.
The choice: Enabled or Disabled.
uSDWCLK CONTROL MA/SRAS
This item controls the phase of SDWCLK used for MA/ SRAS signals that lags ahead SDCLK.
The choice:
uSDWCLK CONTROL DQM/MD
This item controls the phase of SDWCLK used for DQM/MD signals that lags ahead SDCLK.
The choice:
uEGMRCLK CONTROL
This item controls the phase of EGMRCLK that lags behind
SDCLK.
The choice:
uEGMWCLK CONTROL
This item controls the phase of EGMWCLK that lags ahead
SDCLK.
The choice:
APOLLO 120/150 III |
