Emerson MITX-440-DVI-2E, MITX-430 manual 12.2 ICH8-M Gpio, ICH8-M Gpio Definition

Functional Description

4.12.2 ICH8-M GPIO

Table 4-3describes the ICH8-M GPIO definition.

Table 4-3 ICH8-M GPIO Definition

			Power
Name	Type	Tolerance	Well	Default	Signal Description	Implementation
GPIO0	I/O	3.3V	Core	GPI	Multiplexed with	Unused, PU VCC3V3
					BM_BUSY#
GPIO1	I/O	3.3V	Core	GPI	Multiplexed with	Used as IDE 80 pin
					TACH1	cable detect
GPIO2	I/OD	5V	Core	GPI	Multiplexed with	Unused, PU VCC3V3
					PIRQ[H:E]#
GPIO3	I/OD	5V	Core	GPI	Multiplexed with	Unused, PU VCC3V3
					PIRQ[H:E]#
GPIO4	I/OD	5V	Core	GPI	Multiplexed with	Unused, PU VCC3V3
					PIRQ[H:E]#
GPIO5	I/OD	5V	Core	GPI	Multiplexed with	Unused, PU VCC3V3
					PIRQ[H:E]#
GPIO6	I/O	3.3V	Core	GPI	Unmultiplexed	Used for board ID, PU
						VCC3V3
GPIO7	I/O	3.3V	Core	GPI	Unmultiplexed	Used for board ID, PU
						VCC3V3
GPIO8	I/O	3.3V	Resume	GPI	Unmultiplexed	Used as BIOS write
						protect (WP) signal, PU
						VCC3V3DUAL
GPIO9	I/O	3.3V	Resume	GPI	Multiplexed with	Unused, PU
					WOL_EN	VCC3V3DUAL
GPIO10	I/O	3.3V	Resume	GPI	Multiplexed with	Unused, PU
					SusPwrAck/ALERT#	VCC3V3DUAL
GPIO11	I/O	3.3V	Resume	Native	Multiplexed with	Used for SMBus alert
					SMBALERT#	signal, PU
						VCC3V3DUAL

64 MITX-430/MITX-440-DVI-2E Installation and Use Guide (6806800K37B)