Emerson MITX-430, MITX-440-DVI-2E

Functional Description

MITX-430/MITX-440-DVI-2E Installation and Use Guide (6806800K37B)

The RTC also supports two lockable memory ranges. By setting bits in the configuration space,

two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized

reading of passwords or other system security information.

The RTC also supports a data alarm that allows for scheduling a wakeup event up to 30 days in

advance, rather than just 24 hours in advance.

Contents

Main Trademarks Notice Limited and Restricted Rights Legend Contact Address Contents Page Page Page List of Tables List of Tables Page Page List of Figures Page About this Manual Overview of Contents Abbreviations Page Page Page Conventions The following table describes the conventions used throughout this manual. Summary of Changes Comments and Suggestions Page Page Chapter 1 Introduction 1.1 Features 1.1.1 MITX-430 Table 1-1 Single Core Processor Board Features (continued) 1.1.2 MITX-440-DVI-2E The following table lists the features of the dual core processor board: Table 1-1 Single Core Processor Board Features (continued) Table 1-2 Dual Core Processor Board Features Table 1-2 Dual Core Processor Board Features (continued) 1.2 Standard Compliances MITX-430/MITX-440-DVI-2E meets the following standards. Table 1-2 Dual Core Processor Board Features (continued) Table 1-3 Standard Compliances Page 1.3 Mechanical Data 1.4 Ordering Information 1.4.1 Supported Board Models 1.4.2 Board Accessories 1.5 Product Identification Page Page Chapter 2 Hardware Preparation and Installation 2.1 Environmental and Power Requirements 2.1.1 Environmental Requirements 2.1.2 Thermal Requirements 2.1.3 Power Requirements (Single Core Processor Board) 2.1.3.1 Full Loading Running Burn-in Test 2.1.3.2 Idle Mode Power Consumption 2.1.3.3 Standby Mode Power Consumption 2.1.3.3.1 S3 Sleep Mode 2.1.4 Power Requirements (Dual Core Processor Board) 2.1.4.1 Full Loading Running Burn-in Test 2.1.4.2 Idle Mode Power Consumption 2.2 Board Thermal Management and Placement 2.2.1 Board Thermal Management Page 2.3 Unpacking and Inspecting the Board 2.4 Preparing the Installation Environment 2.5 Processor Cooler Installation and Removal 2.6 Memory Module Installation and Removal Page Page Page Page 3.2 Connectors The following subsections describe the connectors used on the board. 3.2.2 LVDS Header (J5) 3.2.1 Clear CMOS (P3) Table 3-1 Clear CMOS 3.2.3 LVDS Backlight Header (P23) 3.2.4 LVDS Power 3.2.5 MINI IDE Header (J8) Header P5 selects the power of LCD Panel. Table 3-3 LVDS Backlight Header PIn Definition 3.2.6 USB Flash Header (P10) Table 3-5 MINI IDE Header PIN Definition (continued) Table 3-6 USB Flash Header Pin Definition 3.2.7 USB Header (P12) 3.2.8 ELO Touch Screen Header (P6) Table 3-6 USB Flash Header Pin Definition (continued) Table 3-7 USB Header Pin Definition Table 3-8 ELO Touch Screen Header Pin Definition 3.2.9 GPIO Header (P4) 3.2.10 COM Header (P9, P27) 3.2.11 RS-232/422/485 (P18) Table 3-9 GPIO Header Pin Definition Table 3-10 COM3, COM6 Header Pin Definition 3.2.12 Power COM (P8, P26) Table 3-12 RS-232/422/485 Jumper Selection (P28) Table 3-11 RS-232/422/485 Header Pin Definition (continued) Table 3-13 COM4, COM5 Header Pin Definition Table 3-14 COM4, COM5 Pin9 Selection 3.2.13 TPM Header (P2) Table 3-14 COM4, COM5 Pin9 Selection (continued) Table 3-15 TPM Header Pin Definition 3.2.14 LPT Header (P11) 3.2.15 Front Panel Header (P15) Table 3-16 LPT Header Pin Definition Table 3-17 Front Panel Header Pin Definition 3.2.16 BIOS Program Header (P16) 3.2.17 Fan Header (P1, P13) Table 3-17 Front Panel Header Pin Definition (continued) Table 3-18 BIOS Program Header Pin Definition Table 3-19 Smart Fan Header Pin Definition 3.2.18 MINI PCIE LED (P14) 3.2.19 Case Open Header (P25) Table 3-20 MINI PCIE Wireless LAN LED Header Pin Definition Table 3-21 Case Open Header Pin Definition Chapter 4 Functional Description SO-DIMM 4.1 Block Diagram 4.2 Pineview-D Processor 4.3 SMBus Interface and Devices Page 4.4 System Memory 4.5 Ethernet Interfaces 4.6 PCI-E Port 4.7 USB Interface 4.8 VGA, LVDS, LPC, and Audio Interface 4.9 DVI Interface 4.10 BIOS Device 4.11 IDE 4.12 GPIO Configuration 4.12.1 User Defined GPIO 4.12.2 ICH8-M GPIO Table 4-3 describes the ICH8-M GPIO definition. Table 4-3 ICH8-M GPIO Definition Page Page Page 4.13 Chipset 4.14 Clock Generator 4.15 Video 4.16 Storage 4.17 Super I/O 4.18 HW Monitor 4.19 SPI Flash Page Page Chapter 5 Operation 5.1 POST 5.2 Boot Process 5.3 Initiating Setup 5.4 Setup Utility 5.4.1 Main Menu 5.4.2 Advanced Menu Table 5-2 Main Menu (continued) Table 5-3 Legacy OPROM Support Table 5-4 Advanced Menu Table 5-5 ACPI Settings Table 5-6 Trusted Computing Table 5-4 Advanced Menu (continued) Table 5-7 S5 RTC Wake Setting Table 5-8 CPU Configuration Table 5-6 Trusted Computing (continued) Table 5-9 IDE Configuration Table 5-8 CPU Configuration (continued) Table 5-10 IGD-LCD Control Table 5-9 IDE Configuration (continued) Table 5-11 USB Configuration Table 5-10 IGD-LCD Control (continued) Table 5-12 EMC2103 H/W Monitor Table 5-13 Super IO Configuration Table 5-14 Serial Port 1 Configuration Table 5-15 Serial Port 2 Configuration Table 5-16 Serial Port 3 Configuration Table 5-17 Serial Port 4 Configuration Table 5-18 Serial Port 5 Configuration Table 5-19 Serial Port 6 Configuration Table 5-20 Parallel Port Configuration Table 5-21 Watchdog Timer Configuration Table 5-22 W83627UHG H/W Monitor Table 5-23 Serial Port Console Redirection Table 5-24 COM1 and COM2 Console Redirection Settings Table 5-23 Serial Port Console Redirection (continued) Table 5-24 COM1 and COM2 Console Redirection Settings (continued) 5.4.3 Chipset Menu Table 5-25 Chipset Menu Table 5-26 Host Bridge Table 5-27 South Bridge 5.4.4 Boot Menu Table 5-27 South Bridge (continued) Table 5-28 Boot Menu 5.4.5 Security Menu 5.4.6 Save & Exit Menu Table 5-28 Boot Menu (continued) Table 5-29 Security Menu Table 5-30 Save & Exit Menu 5.5 POST Codes 5.5.1 Status Code Ranges Table 5-30 Save & Exit Menu (continued) Table 5-31 Status Code Ranges 5.5.2 Standard Status Codes 5.5.2.1 SEC Status Codes Table 5-32 SEC Status Codes 5.5.2.2 PEI Status Codes Table 5-33 PEI Status Codes Page Page 5.5.2.3 PEI Beep Codes Table 5-34 PEI Beep Codes 5.5.2.4 DXE Status Codes Table 5-35 DXE Status Codes Page Page 5.5.2.5 DXE Beep Codes 5.5.2.6 CPU Exception Status Codes Table 5-36 DXE Beep Codes Table 5-37 CPU Exception Status Codes 5.5.2.7 ASL Status Codes Table 5-37 CPU Exception Status Codes (continued) Table 5-38 ASL Status Codes 5.5.2.8 OEM-Reserved Status Code Ranges Table 5-38 ASL Status Codes (continued) Table 5-39 OEM-Reserved Status Code Ranges Page Chapter 6 Operating System and Driver Support 6.1 Supported Operating System 6.2 Supported Drivers Page Appendix A A.1 Emerson Embedded Communications Computing Documents A.2 Related Specifications Related Documentation Table A-2 Related Specifications (continued) Safety Notes EMC VCCI Installation Page Page Operation Page Page Configuration Switches/Jumpers Grounding Connectors and Cabling Page PEM Page Fans/B lower s Page Expansion and FRU Replacement Page Hot Swap PMC Modules SFP/SFP+ Modules Laser Battery Page Page Page Sicherheitshinweise EMC VCCI System Installation Page Page Betrieb Page Page Page Schaltereinstellungen Erdung Stecker und Verkabelung Page PEM Page Lfter Page Erweiterung und FRU Austausch Page Hot Swap PMC Module SFP/SFP+ Modules Laser Batterie Page Page Index A B C Page Page HOW TO REACH LITERATURE AND TECHNICAL SUPPORT: