2635A
Users Manual
4-24
Table 4-5. Command and Query Reference (cont)
*IDN? Identification Query
Returns the instrument identification code.
The identification code consists of four descriptive fields separated by
commas. Note that commas are reserved as field separators and cannot
be used within the fields.
FIELD DESCRIPTION
1 Manufacturer’s name (FLUKE).
2 Instrument model number (2620A or 2625A).
3 0
4 Firmware revision levels.
This query must be the last query on the input line, otherwise a query error
is generated. It is legal to follow this query with other commands.
Example: *IDN? returns FLUKE, 2635A, 0, M6.E A4.7 D1.L1.6 {Fluke
product 2645A is running the main software version M6.2, Analog-to-
Digital Converter software version A4.7, display software version D1.0,
and programmable gate-array version L1.6.]
*OPC Operation Complete
Causes the instrument to generate an Operation Complete when parsed.
*OPC? Operation Complete Query
Causes the instrument to place an ASCII 1 in the output queue when
parsed.
*RST Reset
Performs a Configuration Reset. The RS-232 computer interface
parameters are not changed, and the temperature unit (°C or °F) is not
changed.
*SRE Service Request Enable
Sets the Service Request Enable Register to the given value.
*SRE <value>
<value> = (0 .. 255)
The SRE register is used to enable or disable (mask) the output bits of the
Status Byte Register (STB). The ORed output of the SRE and STB is the
Master Summary Status (MSS) bit, which is used to signal the selected
status bits have been set. See the previous discussion on status registers
for more information. Note that bit 6 cannot be configured, and bits 1, 2, 3,
and 7 are not used.
Example: *SRE 49 [Enables the STB byte 00110001 (decimal 49), which
means the MSS bit is set logic high by an IEB bit -r-MAV bit -or- ESB bit.]
*SRE? Service Request Enable Query
Returns the integer value of the Service Request Enable Register (SRE).
See the discussion on status registers for more information.
Example: *SRE? returns 32 [The SRE register is set for 00100000
(decimal 32), which means the Master Summary Bit will be set logic high
when the ESB bit is set logic high.]