Fujitsu F2MC-8FX manual Table B-1 Bus Operation List 4/11

					APPENDIX B Bus Operation List
Table B-1	Bus Operation List (4/11)
CODE	MNEMONIC	~	Cycle	Address bus	Data bus	RD	WR	RMW
F4	XCHW A, PC	3	1	N +2	Data of N +2	1	0	0
			2	Address divergence	The following	1	0	0
					instruction
			3	Address divergence	The following	1	0	0
				+1	following instruction
A0 - A7	CLRB dir:n	4	1	N +2	The following	1	0	1
					instruction
A8 - AF	SETB dir:n		2	dir address	Data	1	0	1
			3	dir address	Data	0	1	0
			4	N +3	The following	1	0	0
					following instruction
B0 - B7	BBC dir:n, rel	Divergence
B8 - BF	BBS dir:n, rel	5	1	N +2	rel	1	0	0
			2	dir address	Data	1	0	0
			3	N +3	Data of N+3	1	0	0
			4	Address divergence	The following	1	0	0
					instruction
			5	Address divergence	The following	1	0	0
				+1	following instruction
		No divergence
		5	1	N +2	rel	1	0	0
			2	dir address	Data	1	0	0
			3	N +3	The following	1	0	0
					instruction
			4	−	−	0	0	0
			5	N +4	The following	1	0	0
					following instruction
60	MOV A, ext	4	1	N +2	ext (L byte)	1	0	0
			2	N +3	The following	1	0	0
					instruction
			3	ext address	Data	1	0	0
			4	N +4	The following	1	0	0
					following instruction
61	MOV ext, A	4	1	N +2	ext (L byte)	1	0	0
			2	N +3	The following	1	0	0
					instruction
			3	ext address	Data	0	1	0
			4	N +4	The following	1	0	0
					following instruction

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