Fujitsu F2MC-8FX manual Interrupt Enable/Disable and Interrupt Priority Functions

CHAPTER 4 INTERRUPT PROCESSING

4.2Interrupt Enable/Disable and Interrupt Priority Functions

In the F2MC-8FX series, interrupt requests are transferred to the CPU using the three types of enable/disable functions listed below.

•Request enable check by interrupt enable flags in resources

•Checking the level using the interrupt level determination function

•Interrupt start check by the I flag in the CPU

Interrupts generated in resources are transferred to the CPU with the priority levels determined by the interrupt priority function.

■Interrupt Enable/Disable Functions

•Request enable check by interrupt enable flags in resources

This is a function to enable/disable a request at the interrupt source. If interrupt enable flags in resources are enabled, interrupt request signals are sent from resources to the interrupt controller. This function is used for controlling the presence or absence of an interrupt, resource-by-resource. It is very useful because when software is described for each resource operation, interrupts in another resource do not need to be checked for whether they are enabled or disabled.

•Checking the level using the interrupt level determination function

This function determines the interrupt level. The interrupt levels corresponding to interrupts generated in resources are compared with the IL bit in the CPU. If the value is less than the IL bit, a decision is made to issue an interrupt request. This function is able to assign priorities if there are two or more interrupts.

•Interrupt start check by the I flag in the CPU

The I flag enables or disables the entire interrupt. If an interrupt request is issued and the I flag in the CPU is set to interrupt enable, the CPU temporarily suspends the flow of instruction execution to process interrupts. This function is able to temporarily disable the entire interrupt.

■Interrupt Requests in Resources

As shown in Figure 4.2-1,interrupts generated in resources are converted by the corresponding interrupt level registers in the interrupt controller into the values set by software and then transferred to the CPU.

The interrupt level is defined as high if its numerical value is lower, and low if it is higher.

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