APPENDIX |
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Table | Bus Operation List (11/11) |
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CODE | MNEMONIC | ~ |
| Cycle | Address bus | Data bus | RD | WR | RMW |
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− | INTERRUPT | 9 |
| 1 | N +2 | Data of N +2 | 1 | 0 | 0 |
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| 2 | Vector address | Vector (H) | 1 | 0 | 0 |
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| 3 | Vector address +1 | Vector (L) | 1 | 0 | 0 |
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| 4 | SP | Return address (L) | 0 | 1 | 0 |
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| 5 | SP | Return address (H) | 0 | 1 | 0 |
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| 6 | SP | PSL (CCR) | 0 | 1 | 0 |
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| 7 | SP | PSH (RP, DP) | 0 | 1 | 0 |
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| 8 | Address divergence | The following | 1 | 0 | 0 |
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| ahead | instruction |
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| 9 | Address divergence | The following | 1 | 0 | 0 |
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| ahead +1 | following instruction |
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N:Address where instruction under execution is stored Note:
The cycle of the instruction might be extended by the immediately preceding instruction by one cycle. Moreover, cycle of the instruction number might be extended in the access to the IO area.
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