Fujitsu F2MC-8FX manual Table B-1 Bus Operation List 5/11

APPENDIX
Table B-1	Bus Operation List (5/11)
CODE	MNEMONIC	~	Cycle	Address bus	Data bus	RD	WR	RMW
C4	MOVW A, ext	5	1	N +2	ext (L byte)	1	0	0
			2	N +3	The following	1	0	0
					instruction
			3	ext address	Data (H byte)	1	0	0
			4	ext+1 address	Data (L byte)	1	0	0
			5	N +4	The following	1	0	0
					following instruction
D4	MOVW ext, A	5	1	N +2	ext (L byte)	1	0	0
			2	N +3	The following	1	0	0
					instruction
			3	ext address	Data (H byte)	0	1	0
			4	ext+1 address	Data (L byte)	0	1	0
			5	N +4	The following	1	0	0
					following instruction
C5	MOVW A, dir	4	1	N +2	The following	1	0	0
					instruction
			2	dir address	Data (H byte)	1	0	0
			3	dir+1 address	Data (L byte)	1	0	0
			4	N +3	The following	1	0	0
					following instruction
D5	MOVW dir, A	4	1	N +2	The following	1	0	0
					instruction
			2	dir address	Data (H byte)	0	1	0
			3	dir+1 address	Data (L byte)	0	1	0
			4	N +3	The following	1	0	0
					following instruction
C6	MOVW A,	4	1	N +2	The following	1	0	0
	@IX+off				instruction
			2	N +3	The following	1	0	0
					following instruction
			3	(IX)+off address	Data (H byte)	1	0	0
			4	(IX)+off+1 address	Data (L byte)	1	0	0
D6	MOVW @IX+off,	4	1	N +2	The following	1	0	0
	A				instruction
			2	N +3	The following	1	0	0
					following instruction
			3	(IX)+off address	Data (H byte)	0	1	0
			4	(IX)+off+1 address	Data (L byte)	0	1	0

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