Host Interface
Table 4.33 Transfer setting values in the SC register
Transfer mode | Bits 7 to 3 | bits 2 to 0 |
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PIO default transfer mode | 00000 | 000 |
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PIO default transfer mode (without IORDY signal) | 00000 | 001 |
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PIO flow control transfer mode (with IORDY signal) | 00001 | Mode |
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Undefined | 00010 | ∀ |
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Multiword DMA transfer mode | 00100 | Mode |
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Ultra DMA transfer mode | 01000 | Mode |
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Undefined | 10000 | ∀ |
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Mode indicates the number of transfer modes. |
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When the FR register is 95h, the ODD responds with the following value at the end of the command.
Table 4.34 Cylinder Low register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Version (00h)
Table 4.35 Cylinder High register
Bit | 7 | Bit | 6 | Bit | 5 | Bit | 4 | Bit | 3 | Bit 2 | Bit 1 | Bit 0 |
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0 |
| 0 |
| 0 |
| 0 |
| 0 |
| PEJ (1) | LOCK (1) | PENA |
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PENA: Set to 1 when the media status notification function is enabled.