4.7 Timing
Table 4.119 Ultra DMA data out transfer parameter
Symbol | Timing parameter | min | max | Condition |
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| (Units: ns) | (Units: ns) |
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t2CYCTYP | Average | 120 | - | Mode 2 |
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tCYC | Cycle time (for | 54 | - |
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| clock change) |
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t2CYC | 115 | - |
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tDS | Data setup time on receiving side | 7 | - |
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tDH | Data hold time on receiving side | 5 | - |
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tDVS | Data enabled setup time on sending side | 30 | - |
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tDVH | Data enabled hold time | 6 | - |
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tFS | First strobe time | 0 | 170 |
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tLI | Restricted interlock time | 0 | 150 |
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tMLI | Minimum interlock time | 20 | - |
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tUI | 0 | - |
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tAZ | Driver Maximum release time | - | 10 |
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tZAH | Output delay time | 20 | - |
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tZAD | Driver Assert and negate time | 0 | - |
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tENV | Envelope time | 20 | 70 |
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tSR | STROBE to DMARDY time | - | 20 |
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tRSF | Ready to the last STROBE time | - | 60 |
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tRP | Ready to stop time | 100 | - |
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tIORDYZ | Maximum IORDY release time | - | 20 |
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tIORDDY | STROBE operation minimum time | 0 | - |
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tACK | DMACK- setup and hold time | 20 | - |
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tSS | STROBE edge to DMARQ negate and | 50 | - |
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| assert time |
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