Fujitsu MHJ2181AT, MHK2060AT, MHK2090AT, MHK2120AT

5.6 Timing

C141-E088-01EN 5-109

5.6.3.5 Device terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note: The definitions for the STOP, HDMARDY- and DSTROBE signal

lines are no longer in effect after DMARQ and DMACK are

negated.

Figure 5.15 Device terminating an Ultra DMA data in burst

Contents

Main FOR SAFE OPERATION Page Page Page Preface Overview of Manual Conventions for Alert Messages Operating Environment Attention Page Page Important Alert Items Important Alert Messages Page Manual Organization Page Contents CHAPTER 1 Device Overview........................................................................1-1 CHAPTER 2 Device Configuration................................................................ 2-1 CHAPTER 3 Installation Conditions..............................................................3-1 CHAPTER 4 Theory of Device Operation......................................................4-1 Page Page Page Illustrations Figures Tables Page CHAPTER 1 Device Overview 1.1 Features 1.1.1 Functions and performance 1.1.2 Adaptability 1.1.3 Interface Device Overview 1-4C141-E088-01EN 1.2 Device Specifications 1.2.1 Specifications summary 1.2.2 Model and product number 1.3 Power Requirements Page 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.9 Media Defects Page 2.1 Device Configuration Page 2.2 System Configuration 2.2.1 ATA interface 2.2.2 1 drive connection 2.2.3 2 drives connection Page Page Page Page Page 3.2 Mounting Page Page Page Page 3.3 Cable Connections 3.3.1 Device connector 3.3.2 Cable connector specifications 3.3.3 Device connection 3.4 Jumper Settings 3.4.2 Factory default setting 3.4.3 Master drive-slave drive setting 3.4.4 CSEL setting Page CHAPTER 4 Theory of Device Operation 4.1 Outline 4.2 Subassemblies 4.2.1 Disk 4.2.2 Head 4.2.3 Spindle 4.2.4 Actuator 4.2.5 Air filter 4.3 Circuit Configuration Page 4.4 Power-on Sequence 4.5 Self-calibration 4.5.1 Self-calibration contents 4.5.2 Execution timing of self-calibration 4.5.3 Command processing during self-calibration 4.6 Read/write Circuit 4.6.1 Read/write preamplifier (PreAMP) 4.6.2 Write circuit Page 4.6.3 Read circuit 4.6.4 Digital PLL circuit 4.7 Servo Control 4.7.1 Servo control circuit Page Page Page 4.7.2 Data-surface servo format 4.7.3 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control Page Page CHAPTER 5 Interface 5-2C141-E088-01EN 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Figure 5.1 Interface signals 5.1.2 Signal assignment on the connector Page Page 5.2 Logical Interface 5.2.1 I/O registers 5.2.2 Command block registers Page Page Page Page 5.2.3 Control block registers 5.3 Host Commands 5.3.1 Command code and parameters Page 5.3.2 Command descriptions Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page [ Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 5.3.3 Error posting 5-78 C141-E088-01EN Table 5.15 Command code and parameters (2 of 2) 5.4 Command Protocol 5.4.1 Data transferring commands from device to host Page 5.4.2 Data transferring commands from host to device Page 5.4.3 Commands without data transfer 5.4.4 Other commands 5.4.5 DMA data transfer commands Page 5.5 Ultra DMA Feature Set 5.5.1 Overview 5.5.2 Phases of operation Page 5.5.3 Ultra DMA data in commands Page Page Page Page 5.5.4 Ultra DMA data out commands Page Page Page Page Page 5.5.6 Series termination required for Ultra DMA Page Page Page 5.6.3 Transfer of Ultra DMA data 5.6 Timing C141-E088-01EN 5-105 5-106 C141-E088-01EN Table 5.18 Ultra DMA data burst timing requirements (2 of 2) Page Page Page Page Page Page Page Page Page 5.6.4 Power-on and reset Page 6.1 Device Response to the Reset 6.1.1 Response to power-on Page 6.1.2 Response to hardware reset 6.1.3 Response to software reset 6.1.4 Response to diagnostic command 6.2 Address Translation 6.2.1 Default parameters 6.2.2 Logical address 6.3 Power Save 6.3.1 Power save mode Page 6.3.2 Power commands 6.4 Defect Management 6.4.1 Spare area 6.4.2 Alternating defective sectors Page 6.5 Read-Ahead Cache 6.5.1 Data buffer configuration 6.5.2 Caching operation 6.5.3 Usage of read segment Page Page Page Page Page 6.6 Write Cache Page Page Glossary Page Page Page Acronyms and Abbreviations Page Index Page Page Page Page Comment Form