Fujitsu MHK2060AT, MHK2120AT Ultra DMA data in commands, Initiating an Ultra DMA data in burst

5.5 Ultra DMA Feature Set

f)Once the transmitting side has outputted the ending request, the output state of STROBE signal should not be changed unless the receiving side has confirmed it. Then, if the STROBE signal is not in asserted state, The transmitting side should assert the STROBE signal. However, the assertion of the STROBE signal should not cause the data transfer to occur.

g)The transmitting side should return the STROBE signal to its asserted state immediately after receiving the ending request from the receiving side.

However, the returning of the STROBE signal to its asserted state should not cause the data transfer to occur and CRC to be perform.

h)Once the receiving side has outputted the ending request, the negated state of the DMARDY signal should not be changed for the remaining Ultra DMA burst to be performed.

i)The receiving side should neglect the inversion of the STROBE signal if DMARQ signal has been negated or STOP signal has been asserted.

5.5.3 Ultra DMA data in commands

5.5.3.1 Initiating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.1 and 5.6.4.2 for specific timing requirements):

1)The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2)The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE.

3)Steps (3), (4) and (5) may occur in any order or at the same time. The host shall assert STOP.

4)The host shall negate HDMARDY-.

5)The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6)Steps (3), (4) and (5) shall have occurred at least tACK before the host asserts DMACK-. The host shall keep DMACK- asserted until the end of an Ultra DMA burst.

7)The host shall release DD (15:0) within tAZ after asserting DMACK-.

8)The device may assert DSTROBE tZIORDY after the host has asserted DMACK-. Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst.

C141-E088-01EN 5-89