Galil DMC-13X8 user manual Communication with Controller Secondary Fifo channel, Polling Fifo

Send 01H to N+3 address Send 80H to N+3 address Send 01H to N+3 address Send 80H to N+3 address

Read N+3 address (Bit 7 will be 1)

It is a good idea to clear any control data before attempting this procedure. Send a no-op instruction, by reading N+3 address, before you start. All data, including data from the DMC-13X8, will then be cleared.

Clearing the FIFO is useful for emergency resets or Abort. For example, to Reset the controller, clear the FIFO, then send the RS command.

Communication with Controller - Secondary FIFO channel

The DMC-13X8 secondary communication channel is used as a Polling FIFO to provide a status record on demand.

In this mode, the record is in binary format and contains information on position, position error, torque, velocity, switches, inputs, outputs and status. The secondary communication is NOT ACTIVE by default and must be enabled with the DR command which activates the polling FIFO and sets the rate of data update.

Polling FIFO

The Polling FIFO mode puts a record into the secondary FIFO of the controller at a fixed rate. The data should be retrieved from the FIFO using the specific handshake procedure provided below. To prevent conflicts, this procedure does not allow the FIFO to be updated while being read. If the data is not read, the FIFO is updated with new data.

The polling FIFO mode is activated with the command DR-n where n sets the FIFO update rate. This rate is 2n samples between updates. DR 0 turns off the Polling FIFO mode.

Polling Mode Read Procedure

1.Read bit 2 of address N+7 until it is equal to 1. When it is 1 data is available for reading off the 2nd FIFO

2.Send 00H to address N+5. This will prevent the controller from updating the record once the current record has been sent to the 2nd FIFO.

3.Read bit 0 of address N+7 until it is 0. This bit is set to zero by the controller when the data record has been sent to the 2nd FIFO and is ready to be read.

4.Read byte at address N+5. This is the data.

5.Repeat step 4 until all of the desired records have been read. Do not read past the end of the data record - this condition can be tested by monitoring the 'Not Empty' status bit. This can be done by reading bit 2 of address N+7. If this bit is equal to 1, the FIFO is not empty. If this bit is 0, the FIFO is empty. The status byte is described below.

6.Send 00H to address N+5. This allows the controller to resume updating the record.

Note: Data loss can occur if the above procedure is not followed.

USER MANUAL Chapter 4 Communication • 47