Galil DMC-13X8 DMA / Secondary Fifo Memory Map, Overview of Secondary Fifo Procedure, Addr Type

Overview of Secondary FIFO Procedure:

When using the Secondary FIFO, the user reads the 8-bit data and 8-bit status values at the address

N+5 and N+7 (N is the base communication address). The status byte consists of 3 bits of information. Bit 0 is the 'busy' bit, Bit 1 is the 'freeze' bit and Bit 2 is the 'not empty' bit. The additional bits are not used. The following is an explanation of these three status bits:

Bit 0 (Busy Bit) - A '1' signifies that the controller is still sending data to the FIFO. The controller sets this bit to 0 when it is done.

Bit 1 (Freeze Bit) - This bit is '1' when the controller is not sending data to the FIFO and '0' when the controller is sending data to the FIFO. When any value is written to the register N+7, this bit will be set to '1' and the controller will send the rest of the current record then stop sending data to the FIFO. When any value is written to the register N+5, the freeze bit will be set to '0' and the controller will resume its updates to the FIFO. The record must be frozen while reading the record so that it does not change during the read.

Bit 2 (Not Empty Bit) - When this bit is set to '1' by the controller, there is data in the FIFO to be read.

Operation	Register (address)	Value
Read	N+5	Data Byte
Read	N+7	Status Byte
		bit 0 = busy
		bit 1	= freeze
		bit 2	= not empty
		bit 3- 7 = Not Used
Write	N+5	Any Value - Sets freeze bit
Write	N+7	Any Value - Clears freeze bit

DMA / Secondary FIFO Memory Map

ADDR	TYPE	ITEM
00-01	UW	sample number
02	UB	general input 0
03	UB	general input 1
04	UB	general input 2
05	UB	general input 3
06	UB	general input 4
07	UB	general input 5
08	UB	general input 6
09	UB	general input 7
10	UB	general input 8
11	UB	general input 9
12	UB	general output 0
13	UB	general output 1
14	UB	general output 2
15	UB	general output 3
16	UB	general output 4
17	UB	general output 5
18	UB	general output 6

Chapter 4 Communication • 48 USER MANUAL