Hitachi HTS543216L9A300, HTS543232L9A300, HTS543280L9SA00, HTS543225L9A300 14.14Read DMAC8h/C9h

Models: HTS543225L9A300 HTS543232L9A300 HTS543216L9A300 HTS543216L9SA00 HTS543212L9A300 HTS543280L9SA00

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14.14Read DMA(C8h/C9h)

5K320 SATA OEM Specification

14.14Read DMA(C8h/C9h)

Command Block Output Registers

 

 

 

 

 

 

Command Block Input Registers

 

 

 

 

 

 

 

Register

7

6

5

4

3

2

1

0

Register

7

6

5

4

3

2

1

0

Data

-

-

-

-

-

-

-

-

Data

-

-

-

-

-

-

-

-

Feature

-

-

-

-

-

-

-

-

Error

 

 

...See Below...

 

 

Sector Count

V V V V V V V V

Sector Count

V V V V V V

V V

LBA Low

V V V V V V V V

LBA Low

V V V V V V

V V

LBA Mid

V V V V V V V V

LBA Mid

V V V V V V

V V

LBA High

V V V V V V V V

LBA High

V V V V V V

V V

Device

-

L

-

- H H H H

Device

-

-

-

-

H

H

H

H

Command

1

1

0

0

1

0

0

R

Status

 

 

...See Below...

 

 

Error Register

7

6

5

4

3

2

1

0

CRC

UNC

0

IDN

0

ABT

T0N

AM

 

 

 

 

 

 

 

N

VManual backgroundManual background V Manual backgroundManual background 0 Manual backgroundManual background V Manual backgroundManual background 0 Manual backgroundManual background V Manual backgroundManual background 0 Manual backgroundManual background 0 Table 69 Read DMA Command (C8h/C9h)

Status Register

7

6

5

4

3

2

1

0

BSY

RDY

DF

DSC

DRQ

COR

IDX

ERR

0

V

0

V

-

0

0

V

The Read DMA command reads one or more sectors of data from disk media, then transfers the data from the device to the host.

The sectors are transferred through the Data Register 16 bits at a time.

The host initializes a slave-DMA channel prior to issuing the command. The data transfers are qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one interrupt per command to indicate that data transfer has terminated and status is available.

If an uncorrectable error occurs, the read will be terminated at the failing sector.

Output Parameters To The Device

Sector Count

The number of continuous sectors to be transferred. If zero is specified, then 256 sectors

LBA Low

will be transferred.

The sector number of the first sector to be transferred. (L=0)

LBA High/Mid

In LBA mode, this register specifies LBA address bits 0 - 7 to be transferred. (L=1)

The cylinder number of the first sector to be transferred. (L=0)

 

In LBA mode, this register specifies LBA address bits 8 - 15 (Mid) 16 - 23 (High) to be

H

transferred. (L=1)

The head number of the first sector to be transferred. (L=0)

R

In LBA mode, this register specifies LBA bits 24-27 to be transferred. (L=1)

The retry bit, but this bit is ignored.

Input Parameters From The Device

Sector Count

The number of requested sectors not transferred. This will be zero, unless an

LBA Low

unrecoverable error occurs.

The sector number of the last transferred sector. (L=0)

LBA High/Mid

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

The cylinder number of the last transferred sector. (L=0)

 

In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).

H

(L=1)

The head number of the sector to be transferred. (L=0)

 

In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

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Hitachi HTS543216L9A300, HTS543232L9A300, HTS543280L9SA00, HTS543225L9A300, HTS543216L9SA00 manual 14.14Read DMAC8h/C9h