Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
6-16
6.3.2 Write Cycle
Write cycles are of two types:
•Pipelined. Pipelined write cycles are described in “Pipelined Cycle” on page 6-19.
•Nonpipelined. Figure 6-6 shows two nonpipelined write cycles (one with and one without a
wait state).
The sequence of signals for a nonpipelined writ e cycle is as follows:
1. The processor initiates the cycle by driving the address bus and the status signals active
and asserting ADS#. The type of bus cycle occurring is determined by the states of the
address bus (A25:1), byte enable pins (BLE# and BHE#), and bus status outputs (W/ R#,
M/IO#, D/C#, REFRESH#, and LOCK#). Because of output delays, these signals should
be sampled at the rising edge of the CLK2 signal that coincides with the falling edge of
PH2, when ADS# is definitely active. For a write cycle, the bus status outputs have the
following states:
•W/R# is high
•M/IO# is high for a memory write and low for an I/O write
•D/C# is high for a memory write or I/O write cycle. During halt and shutdown cycles,
D/C# is low. Unless D/C# is decoded by external chip-select logic, the shutdown or
halt cycle looks like a memory write cycle to byte address zero or two, respectively.
Therefore, the signal D/C# needs to be decoded for memory device chip-selects in
this address range (normally SRA M or D RA M devices) in order to recognize halt and
shutdown cycles, thus preventing incorrect write cycles to memory
•REFRESH# is deasserted
•LOCK# is asserted for a locked cycle and deasserted for an unl ocked cycle. In a read-
modify-write sequence, both the memory data read and memory data write cycles are
locked. No other bus master should be permitted to control the bus between two
locked bus cycles.
The address bus, byte enable pins, a nd bus s tatus pin s (with the excepti on of A DS# and
WR#) remain active through the end of the write cycle.
2. At the start of Phase 2 in T1, the WR# signal is asserted and the CPU begins to drive
output data on its data pins. The data remains valid until the start of phase 2 in the T-State
after the present bus cycle has terminated.
3. If a chip-select region is enabled for the current read cycle but internal READY#
generation is disabled for that region, and the Chip-select Unit is programme d to insert
wait-states, then the READY# signal is ignored (not sampled) by the processor until the
programmed number of wait-states are inserted into the cycl e.