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Intel 386 - page 286

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11

ASYNCHRONOUS

SERIAL I/O UNIT

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Main Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page TABLES n.......... ................... ................. .................... ................. 10-6 Page Page Page Page CHAPTER 1 GUIDE TO THIS MANUAL Page Page Page Page Page Page Page Page CHAPTER 2 ARCHITECTURAL OVE RV IEW Figure 2-1. Intel386 EX Embedded Processor Block Diagram 2-2 ARCHITECTURAL OVERVIEW Table 2-1. PC-compatible Peripherals Table 2-2. Embedded Application-specific Peripherals IEEE Standard Test Access Port and Boundary-Scan Architect ure Page Page CHAPTER 3 CORE OVERVIEW Page 3-3 CORE OVERVIEW Figure 3-2 shows the internal architecture of the Intel386 CX processor. Figure 3-2. The Intel386 CX Processor Internal Block Diagram Page Page Page Page CHAPTER 4 SYSTEM REGISTER ORGANIZATION Page Figure 4-2. Expanded I/O Address Space (16-bit Decode) Page Page Figure 4-3. Address Configuration Register (REMAPCFG) Page Page Figure 4-5. DOS-Compatible Mode Page Figure 4-6. Example of Nonintrusive DOS-Compatible Mode Figure 4-7. Enhanced DOS Mode Figure 4-8. NonDOS Mode Table 4-2. Peripheral Register Addresses (Sheet 1 of 6) Table 4-2. Peripheral Register Addresses (Sheet 2 of 6) Table 4-2. Peripheral Register Addresses (Sheet 3 of 6) Table 4-2. Peripheral Register Addresses (Sheet 4 of 6) Table 4-2. Peripheral Register Addresses (Sheet 5 of 6) Table 4-2. Peripheral Register Addresses (Sheet 6 of 6) Page Page CHAPTER 5 DEVICE CONFIGURATION Page Figure 5-2. Configuration of DMA, Bus Arbiter, and Refresh Unit Figure 5-3. DMA Configuration Register (DMACFG) Page Table 5-1. Masters IR3 Connections Table 5-2. Masters IR4 Connections Figure 5-4. Interrupt Control Unit Configuration 5-9 Figure 5-5. Interrupt Configuration Register (INTCFG) Page Figure 5-6. Timer/Counter Unit Configuration Figure 5-7. Timer Configuration Register (TMRCFG) Page Figure 5-8. Serial I/O Unit 0 Configuration Figure 5-9. Serial I/O Unit 1 Configuration Figure 5-10. SIO and SSIO Configuration Register (SIOCFG) Figure 5-11. SSIO Unit Configuration Page Figure 5-12. Configuration of Chip-select Unit and Clock and Power Management Unit Figure 5-13. Core Configuration Page Page Figure 5-15. Pin Configuration Register (PINCFG) Figure 5-16. Port 1 Configuration Register (P1CFG) Figure 5-17. Port 2 Configuration Register (P2CFG) Figure 5-18. Port 3 Configuration Register (P3CFG) Page Table 5-4. Example Pin Configuration Registers Table 5-5. Example DMACFG Configuration Register Table 5-6. Example TMRCFG Configuration Register Table 5-7. Example INTCFG Configuration Register Table 5-8. Example SIOCFG Configuration Register Table 5-9. Pin Configuration Register Design Woksheet Table 5-10. DMACFG Register Design Worksheet Table 5-11. TMRCFG Register Design Worksheet Table 5-12. INTCFG Register Design Worksheet Table 5-13. SIOCFG Register Design Worksheet Page Page Page CHAPTER 6 BUS INTERFACE UNIT Page 6.1.1 Bus Signal Descriptions Table 6-1 describes the signals associated with the BIU. Table 6-1. Bus Interface Unit Signals (Sheet 1 of 2) Table 6-1. Bus Interface Unit Signals (Sheet 2 of 2) Page Figure 6-1. Basic External Bus Cycles Page Page Page Page Figure 6-4 shows internal and external bus cycles. Figure 6-4. Basic Internal and External Bus Cycles Page Page Figure 6-5. Nonpipelined Address Read Cycles 6-15 Page Figure 6-6. Nonpipelined Address Write Cycles 6-18 Page Figure 6-7. Complete Bus States (Including Pipelined Address) L H d e Figure 6-8. Pipelined Address Cycles 6-21 Page Figure 6-9. Interrupt Acknowledge Cycles 6-25 Figure 6-10. Halt Cycle 6-27 Page Figure 6-11. Basic Refresh Cycle 6-29 Figure 6-12. Refresh Cycle During HOLD/HLDA 6-30 Page Page Figure 6-13. 16-bit Cycles to 8-bit Devices (Using BS8#) Page Page Page Page Page 6.6.1.1 System Configuration Figure 6-15. Intel386 EX Processor to Intel387 SX Math Coprocessor Interface Page Page Page 6-44 n Figure 6-19. Intel386 EX Processor and Non-Paged DRAM Interface Note: A single mux can be used in place of the row and column address buffers. Page Page CHAPTER 7 SYSTEM MANAGEMENT MODE Page Page Page Page Even if bus cycles are pipelined, the minimum clock numbers are guaranteed. Page Page Page Page Page Page Page Page Page Page Page Page SYSTEM MANAGEMENT MODE Page Page Page CHAPTER 8 CLOCK AND POWER MANAGEMENT UNIT 8-2 Three of the internal peripherals have selectable clock sources. Figure 8-1. Clock and Power Management Unit Connections Page Page CLOCK AND POWER MANAGEMENT UNIT 8.1.2.3 Watchdog Timer Unit Operation During Idle Mode Table 8-1. Clock and Power Management Registers Table 8-2. Clock and Power Management Signals Page Figure 8-5. Power Control Register (PWRCON) Page Page Page Page Page CLOCK AND POWER MANAGEMENT UNIT Page Page Page CHAPTER 9 INTERRUPT CONTROL UNIT Page Figure 9-1. Interrupt Control Unit Configuration 9-3 Page Table 9-1. 82C59A Master and Slave Interrupt Sources Page Page Page Page Figure 9-3. Interrupt Process Master Request from Non-slave Source 9-11 Figure 9-4. Interrupt Process Slave Request 9-12 Figure 9-5. Interrupt Process Master Request from Slave Source 9-13 Table 9-2. ICU Registers(Sheet 1 of 2) Address PC/AT* Address Function Page Figure 9-6. Port 3 Configuration Register (P3CFG) Figure 9-7. Interrupt Configuration Register (INTCFG) Figure 9-8. Initialization Command Word 1 Register (ICW1) Page Page Page Figure 9-12. Initialization Command Word 4 Register (ICW4) Figure 9-13. Operation Command Word 1 (OCW1) Figure 9-14. Operation Command Word 2 (OCW2) Figure 9-15. Operation Command Word 3 (OCW3) Page Page Page Figure 9-19. Cascading External 82C59A Interrupt Controllers 9-31 Page Page Page Page Page Page Page Page Page Page Page Page Page CHAPTER 10 TIMER/COUNTER UNIT 10-2 Figure 10-1. Timer/Counter Unit Signal Connections V PSCLK Table 10-1. TCU Signals Table 10-2. TCU Associated Registers Page Page Figure 10-2. Mode 0 Basic Operation Figure 10-3. Mode 0 Disabling the Count Page Figure 10-5. Mode 1 Basic Operation Figure 10-6. Mode 1 Retriggering the One-shot Figure 10-8. Mode 2 Basic Operation Figure 10-9. Mode 2 Disabling the Count Page Page 86 42 ????42424286 ????864286410 Figure 10-14. Mode 3 Writing a New Count (With a Trigger) Page Figure 10-17. Mode 4 Disabling the Count Figure 10-18. Mode 4 Writing a New Count Page Page Figure 10-22. Timer Configuration Register (TMRCFG) Figure 10-23. Port 3 Configuration Register (P3CFG) Use PINCFG bit 5 to connect TMROUT2, TMRCLK2, and TMRGATE2 to package pins. Figure 10-24. Pin Configuration Register (PINCFG) Page Figure 10-25. Timer Control Register (TMRCON Control Word Format) Table 10-5 lists the minimum and maximum initial counts for each mode. Page Page Read Format) Register (TMR Figure 10-28. Timer 10.3.4.3 Read-back Command Figure 10-29. Timer Control Register (TMRCON Read-back Format) Bit Number Bit Mnemonic Function Page Figure 10-30. Timer Status Format) Register (TMR Page Page Page Page Page Page Page Page Page Page Page Page CHAPTER 11 ASYNCHRONOUS SERIAL I/O UNIT Figure 11-1. Serial I/O Unit 1 Configuration 11.1.1 SIO Signals Table 11-1 lists the SIOn signals. Table 11-1. SIO Signals Page Page Page Page Figure 11-4. SIO n Data Transmission Process Flow 11-8 Page Figure 11-6. SIO n Data Reception Process Flow 11-11 Page Page Page Table 11-5. SIO Registers(Sheet 1 of 2) Table 11-6. Access to Multiplexed Registers Table 11-5. SIO Registers(Sheet 2 of 2) 11.3.1 Pin and Port Configuration Registers (PINCFG and P CFG [ Figure 11-7. Pin Configuration Register (PINCFG) = 13]) Use PINCFG bits 2:0 to connect the SIO1 signals to package pins. Use P1CFG bits 4:0 to connect SIO0 signals to package pins. Figure 11-8. Port 1 Configuration Register (P1CFG) Use P2CFG bits 75 to connect SIO0 signals to package pins. Figure 11-9. Port 2 Configuration Register (P2CFG) Use P3CFG bit 7 to connect the COMCLK pin to the package pin. Figure 11-10. Port 3 Configuration Register (P3CFG) Figure 11-11. SIO and SSIO Configuration Register (SIOCFG) 11.3.3 Divisor Latch Registers (DLL and DLH and DLH Figure 11-12. Divisor Latch Registers (DLL 11.3.4 Transmit Buffer Register (TBR Figure 11-13. Transmit Buffer Register (TBR 11.3.5 Receive Buffer Register (RBR Figure 11-14. Receive Buffer Register (RBR 11.3.6 Serial Line Control Register (LCR Figure 11-15. Serial Line Control Register (LCR 11.3.7 Serial Line Status Register (LSR Use LSRn to check the status of the transmitter and receiver. Figure 11-16. Serial Line Status Register (LSR 11.3.8 Interrupt Enable Register (IER Figure 11-17. Interrupt Enable Register (IER 11.3.9 Interrupt ID Register (IIR Figure 11-18. Interrupt ID Register (IIR Page Figure 11-21. Modem Control Register (MCR 11-30 11.3.11 Modem Status Register (MSR Figure 11-22. Modem Status Register (MSR Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page CHAPTER 12 DMA CONTROLLER Figure 12-1. DMA Unit Block Diagram Page 12.1.2 DMA Signals Table 12-1 describes the DMA signals. Table 12-1. DMA Signals n# As an input: As an output: Page Page Page 12-8 Figure 12-2. DMA Temporary Buffer Operation for a Read Transfer Figure 12-3. DMA Temporary Buffer Operation for A Write Transfer Page Page Figure 12-6. Buffer Transfer Ended by an Expired Byte Count Figure 12-7. Buffer Transfer Ended by the EOP# Input n Page Page Page Figure 12-8. Single Data-transfer Mode with Single Buffer-transfer Mode n Figure 12-9. Single Data-transfer Mode with Autoinitialize Buffer-transfer Mode Figure 12-10. Single Data-transfer Mode with Chaining Buffer-transfer Mode n Page Figure 12-11. Block Data-transfer Mode with Single Buffer-transfer Mode n Figure 12-12. Block Data-transfer Mode with Autoinitialize Buffer-transfer Mode n Page Figure 12-14. Demand Data-transfer Mode with Single Buffer-transfer Mode Figure 12-15. Demand Data-transfer Mode with Autoinitialize Buffer-transfer Mode n Figure 12-16. Demand Data-transfer Mode with Chaining Buffer-transfer Mode n Page Page Page Table 12-3. DMA Registers (Sheet 1 of 3) Write Format Read Format Table 12-3. DMA Registers (Sheet 2 of 3) Table 12-3. DMA Registers (Sheet 3 of 3) Figure 12-18. Pin Configuration Register (PINCFG) Figure 12-19. DMA Configuration Register (DMACFG) Figure 12-20. DMA Channel Address and Byte Count Registers (DMA BYC , DMA TAR , DMA Page Figure 12-22. DMA Command 1 Register (DMACMD1) Figure 12-23. DMA Status Register (DMASTS) Bit Number Bit Mnemonic Function Figure 12-24. DMA Command 2 Register (DMACMD2) Page Figure 12-25. DMA Mode 1 Register (DMAMOD1) Page Figure 12-26. DMA Mode 2 Register (DMAMOD2) Page Figure 12-28. DMA Software Request Register (DMASRR read format) Page Figure 12-30. DMA Group Channel Mask Register (DMAGRPMSK) Figure 12-31. DMA Bus Size Register (DMABSR) Page Figure 12-33. DMA Interrupt Enable Register (DMAIEN) Figure 12-34. DMA Interrupt Status Register (DMAIS) Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page CHAPTER 13 SYNCHRONOUS SERIAL I/O UNIT 13-2 Figure 13-1. Transmitter and Receiver in Master Mode Transmitter 13.1.1 SSIO Signals Table 13-1 lists the SSIO signals. Table 13-1. SSIO Signals Signal Device Pin or Internal Signal Description Serial Clock (SERCLK) Prescaled Clock (PSCLK) Page Page Page Page Figure 13-8. Transmit Data by Polling Figure 13-9. Interrupt Service Routine for Transmitting Data Using Interrupts Page Page Page Figure 13-13. Interrupt Service Routine for Receiving Data Using Interrupts Page Table 13-3. SSIO Registers Address Function Figure 13-15. Pin Configuration Register (PINCFG) Figure 13-16. SIO and SSIO Configuration Register (SIOCFG) 13.3.3 Prescale Clock Register (CLKPRS) Use CLKPRS to program the PSCLK frequency. Figure 13-17. Clock Prescale Register (CLKPRS) Figure 13-18. SSIO Baud-rate Control Register (SSIOBAUD) Page Figure 13-20. SSIO Control 1 Register (SSIOCON1) Figure 13-21. SSIO Control 2 Register (SSIOCON2) Figure 13-22. SSIO Transmit Holding Buffer (SSIOTBUF) Page Page Page Page Page Page Page Page Page Page Page Page CHAPTER 14 CHIP-SELECT UNIT Page Figure 14-2. Determining a Channels Address Block Size Page Page Page Page Page Page Page Figure 14-3. Bus Cycle Length Adjustments for Overlapping Regions Page Table 14-2. CSU Registers Register Expanded Address Description CHIP-SELECT UNIT Figure 14-4. Pin Configuration Register (PINCFG) Figure 14-5. Port 2 Configuration Register (P2CFG) Page Figure 14-7. Chip-select Low Address Register (CS ADL, UCSADL) Page Figure 14-9. Chip-select Low Mask Registers (CS MSKL, UCSMSKL) Page Page CHIP-SELECT UNIT Page Page Page CHAPTER 15 REFRESH CONTROL UNIT Page REFRESH CONTROL UNIT Figure 15-1. Refresh Control Unit Connections Page Page Page Page Figure 15-3. Refresh Control Register (RFSCON) Page Figure 15-5. Refresh Address Register (RFSADD) Page Page Page Figure 15-8. RAS# Only Refresh Logic: Non-Paged Mode Note: A single mux can be used in place of the row and column address buffers. REFRESH CONTROL UNIT Page Page Page CHAPTER 16 INPUT/OUTPUT PORTS Figure 16-1. I/O Port Block Diagram Figure 16-2. Logic Diagram of a Bi-directional Port 16-3 Page Table 16-1. Pin Multiplexing Table 16-2. I/O Port Registers NOTE CFG) Configuration Register (P Figure 16-3. Port You must program both registers to correctly configure the pins. Table 16-3. Control Register Values for I/O Port Pin Configurations Figure 16-4. Port Direction Register (P DIR) LTC) Figure 16-5. Port Data Latch Register (P Figure 16-6. Port Pin State Register (P PIN) Page Page Page Page Page Page Page CHAPTER 17 WATCHDOG TIMER UNIT Page Page Page Page Table 17-2. WDT Registers Register Address Description Figure 17-2. WDT Counter Value Registers (WDTCNTH and WDTCNTL) Figure 17-3. WDT Status Register (WDTSTATUS) Figure 17-4. WDT Reload Value Registers (WDTRLDH and WDTRLDL) Figure 17-5. Power Control Register (PWRCON) Page See Appendix C for included header files. Page Page Page Page Page CHAPTER 18 JTAG TEST-LOGIC UNIT Page Page Page Figure 18-2. TAP Controller (Finite-State Machine) Page Page JTAG TEST-LOGIC UNIT Table 18-5. Boundary-scan Register Bit Assignments Bit Pin Bit Pin Bit Pin Bit Pin Page Page 18-12 Figure 18-5. Internal and External Timing for Loading the Instruction Register 18-13 JTAG TEST-LOGIC UNIT Figure 18-6. Internal and External Timing for Loading a Data Register Page Page Page APPENDIX A SIGNAL DESCRIPTIONS Table A-2. Description of Signals Available at the Device Pins (Sheet 1 of 6) Table A-2. Description of Signals Available at the Device Pins (Sheet 2 of 6) Table A-2. Description of Signals Available at the Device Pins (Sheet 3 of 6) Table A-2. Description of Signals Available at the Device Pins (Sheet 4 of 6) Table A-2. Description of Signals Available at the Device Pins (Sheet 5 of 6) Table A-2. Description of Signals Available at the Device Pins (Sheet 6 of 6) Table A-3 defines the abbreviations used in Table A-4 to describe the pin states. Table A-3. Pin State Abbreviations Table A-4. Pin States After Reset and During Idle, Powerdown, and Hold (Sheet 1 of 2) Table A-4. Pin States After Reset and During Idle, Powerdown, and Hold (Sheet 2 of 2) Page Page APPENDIX B COMPATIBILITY WITH THE PC/AT* ARCHITECTURE Page Page Page Page Page Page APPENDIX C EXAMPLE CODE HEADER FILES Page Page Page Page C.2 EXAMPLE CODE DEFINES Page Page Page Page Page Page Page Page Page Page APPENDIX D SYSTEM REGISTER QUICK REFERENCE D.1 PERIPHERAL REGISTER ADDRESSES Table D-1. Peripheral Register Addresses (Sheet 1 of 6) Table D-1. Peripheral Register Addresses (Sheet 2 of 6) Table D-1. Peripheral Register Addresses (Sheet 3 of 6) Table D-1. Peripheral Register Addresses (Sheet 4 of 6) Table D-1. Peripheral Register Addresses (Sheet 5 of 6) Table D-1. Peripheral Register Addresses (Sheet 6 of 6) D.2 CLKPRS D.3 CS ADH (UCSADH) D.4 CS ADL (UCSADL) D.5 CS MSKH (UCSMSKH) D.6 CS MSKL (UCSMSKL) D.7 DLL AND DLH D.8 DMABSR D.9 DMACFG D.10 DMACHR D.11 DMACMD1 D.12 DMACMD2 D.13 DMAGRPMSK D.14 DMAIEN D.15 DMAIS D.16 DMAMOD1 D.17 DMAMOD2 D.18 DMAMSK n, TAR DMA AND D.20 DMAOVFE D.21 DMASRR D.22 DMASTS D.23 ICW1 (MASTER AND SLAVE) D.24 ICW2 (MASTER AND SLAVE) D.25 ICW3 (MASTER) D.26 ICW3 (SLAVE) D.27 ICW4 (MASTER AND SLAVE) D.28 IDCODE D.29 IER D.30 IIR D.31 INTCFG D.32 IR D.33 LCR D.34 LSR D.35 MCR D-38 D.36 MSR D.37 OCW1 (MASTER AND SLAVE) D.38 OCW2 (MASTER AND SLAVE) D.39 OCW3 (MASTER AND SLAVE) D.40 P1CFG D.41 P2CFG D.42 P3CFG D.43 PINCFG D.44 P DIR D.45 P LTC PIN D.46 P D.47 POLL (MASTER AND SLAVE) D.48 PORT92 D.49 PWRCON D.50 RBR D.51 REMAPCFG D.52 RFSADD D.53 RFSBAD D.54 RFSCIR D.55 RFSCON D.56 SCR D.57 SIOCFG D.58 SSIOBAUD D.59 SSIOCON1 D.60 SSIOCON2 D.61 SSIOCTR D.62 SSIORBUF D.63 SSIOTBUF D.64 TBR D.65 TMRCFG D.66 TMRCON D.67 TMR Page Page D.72 WDTCNTH AND WDTCNTL D.73 WDTRLDH AND WDTRLDL D.74 WDTSTATUS Page Page APPENDIX E INSTRUCTION SET SUMMARY Table E-1. Instruction Set Summary (Sheet 1 of 19) Table E-1. Instruction Set Summary (Sheet 2 of 19) Table E-1. Instruction Set Summary (Sheet 3 of 19) Table E-1. Instruction Set Summary (Sheet 4 of 19) Table E-1. Instruction Set Summary (Sheet 5 of 19) Table E-1. Instruction Set Summary (Sheet 6 of 19) Table E-1. Instruction Set Summary (Sheet 7 of 19) Table E-1. Instruction Set Summary (Sheet 8 of 19) Table E-1. Instruction Set Summary (Sheet 9 of 19) Table E-1. Instruction Set Summary (Sheet 10 of 19) Table E-1. Instruction Set Summary (Sheet 11 of 19) Table E-1. Instruction Set Summary (Sheet 12 of 19) Table E-1. Instruction Set Summary (Sheet 13 of 19) Table E-1. Instruction Set Summary (Sheet 14 of 19) Table E-1. Instruction Set Summary (Sheet 15 of 19) Table E-1. Instruction Set Summary (Sheet 16 of 19) Table E-1. Instruction Set Summary (Sheet 17 of 19) Table E-1. Instruction Set Summary (Sheet 18 of 19) Table E-1. Instruction Set Summary (Sheet 19 of 19) Page Page Page Page E.2.2.3 Encoding of the Segment Register (sreg) Field Table E-5. Encoding of reg Field When w Field is Present in Instruction Table E-6. Encoding of the Segment Register (sreg) Field Page Table E-7. Encoding of 16-bit Address Mode with mod r/m Byte Table E-8. Encoding of 32-bit Address Mode with mod r/m Byte (No s-i-b Byte Present) Table E-9. Encoding of 32-bit Address Mode (mod r/m Byte and s-i-b Byte Present) E.2.2.5 Encoding of Operation Direction (d) Field E.2.2.6 Encoding of Sign-Extend (s) Field E.2.2.7 Encoding of Conditional Test (tttn) Field Table E-10. Encoding of Operation Direction (d) Field Table E-11. Encoding of Sign-Extend (s) Field For the loading and storing of the Control, Debug and Test registers. Table E-13. When Interpreted as Control Register Field Table E-14. When Interpreted as Debug Register Field Table E-15. When Interpreted as Test Register Field Page Page Page GLOSSARY Page Page Page Page Page Page Page INDEX A B C D E F H I J L M N O R Page S T U V W