Intel 386 D.45 P, LTC, PIN, D.46 P

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
D-48
D.45 P n LTC
D.46 P
n PIN
Port Data Latch
P
n LTC ( n =1–3)
(read/write)
Expanded Addr:
ISA Addr:
Reset State:
F862H, F86AH, F872H
—
FFH
7 0
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
Bit
Number Bit Mnemonic Function
7–0 PL7:0 Port Data Latch:
Writing a value to a PL bit causes tha t value to be driven onto the
corresponding pin.
For a complementary output, write the desired pin value to its PL bit.
This value is strongly dri ve n on to the pin.
For an open-drain output, a one results in a high-impedance (inp ut) state
at the pin.
For a high-impedance input, write a one to the corresponding PL bit. A
one results in a high-impedance state at the pin, allowing external
hardware to drive it.
Port Pin State
P
n PIN ( n =1–3)
(read only)
Expanded Addr:
ISA Addr:
Reset State:
F860H, F868H, F870H
—
XXH
7 0
PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0
Bit
Number Bit Mnemonic Function
7–0 PS7:0 Pin Sta te :
Reading a PS bit returns the logic state present on the associated port
pin.